ex7.rpt
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 383 行 · 第 1/2 页
RPT
383 行
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 13/23
Number of signals used by logic mapping into function block: 21
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 46 I/O
(unused) 0 0 0 5 FB4_2 44 I/O
(unused) 0 0 0 5 FB4_3 51 I/O
q<1> 1 0 0 4 FB4_4 STD 52 I/O O
(unused) 0 0 0 5 FB4_5 47 I/O
(unused) 0 0 0 5 FB4_6 54 I/O
(unused) 0 0 0 5 FB4_7 55 I/O
N_q<3>$WA1 2 0 0 3 FB4_8 STD 48 I/O (b)
N_q<3>$WA0 2 0 0 3 FB4_9 STD 50 I/O (b)
N_q<2>$WA1 2 0 0 3 FB4_10 STD 57 I/O (b)
N_q<2>$WA0 2 0 0 3 FB4_11 STD 53 I/O (b)
q<2> 1 0 0 4 FB4_12 STD 58 I/O O
q<3> 1 0 0 4 FB4_13 STD 61 I/O O
q<0> 1 0 0 4 FB4_14 STD 56 I/O O
N_q<1>$WA1 2 0 0 3 FB4_15 STD 65 I/O (b)
N_q<1>$WA0 2 0 0 3 FB4_16 STD 62 I/O (b)
N_q<0>$WA1 2 0 0 3 FB4_17 STD 66 I/O (b)
N_q<0>$WA0 2 0 0 3 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "ain<0>" 8: "bin<3>" 15: "N_q<2>"
2: "ain<1>" 9: "N_q<0>" 16: "N_q<2>$WA0"
3: "ain<2>" 10: "N_q<0>$WA0" 17: "N_q<2>$WA1"
4: "ain<3>" 11: "N_q<0>$WA1" 18: "N_q<3>"
5: "bin<0>" 12: "N_q<1>" 19: "N_q<3>$WA0"
6: "bin<1>" 13: "N_q<1>$WA0" 20: "N_q<3>$WA1"
7: "bin<2>" 14: "N_q<1>$WA1" 21: sel
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q<1> ...........X@@.......................... 3 1
N_q<3>$WA1 ...X................X................... 2 2
N_q<3>$WA0 .......X............X................... 2 2
N_q<2>$WA1 ..X.................X................... 2 2
N_q<2>$WA0 ......X.............X................... 2 2
q<2> ..............X@@....................... 3 1
q<3> .................X@@.................... 3 1
q<0> ........X@@............................. 3 1
N_q<1>$WA1 .X..................X................... 2 2
N_q<1>$WA0 .....X..............X................... 2 2
N_q<0>$WA1 X...................X................... 2 2
N_q<0>$WA0 ....X...............X................... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"N_q<0>" = "N_q<0>$WA0" * "N_q<0>$WA1" ; FC node
"q<0>" = "N_q<0>"
"N_q<0>$WA0" = "bin<0>"
"N_q<0>$WA0".TRST = sel
"N_q<0>$WA1" = "ain<0>"
"N_q<0>$WA1".TRST = /sel
"N_q<1>" = "N_q<1>$WA0" * "N_q<1>$WA1" ; FC node
"q<1>" = "N_q<1>"
"N_q<1>$WA0" = "bin<1>"
"N_q<1>$WA0".TRST = sel
"N_q<1>$WA1" = "ain<1>"
"N_q<1>$WA1".TRST = /sel
"N_q<2>" = "N_q<2>$WA0" * "N_q<2>$WA1" ; FC node
"q<2>" = "N_q<2>"
"N_q<2>$WA0" = "bin<2>"
"N_q<2>$WA0".TRST = sel
"N_q<2>$WA1" = "ain<2>"
"N_q<2>$WA1".TRST = /sel
"N_q<3>" = "N_q<3>$WA0" * "N_q<3>$WA1" ; FC node
"q<3>" = "N_q<3>"
"N_q<3>$WA0" = "bin<3>"
"N_q<3>$WA0".TRST = sel
"N_q<3>$WA1" = "ain<3>"
"N_q<3>$WA1".TRST = /sel
**************************** Device Pin Out ****************************
Device : XC9572-7-PC84
T T T G T T T T T T T T T T T T T V T T T
I I I N I I I I I I I I I I I I I C I I I
E E E D E E E E E E E E E E E E E C E E E
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
TIE | 12 74 | TIE
TIE | 13 73 | VCC
TIE | 14 72 | TIE
TIE | 15 71 | TIE
GND | 16 70 | TIE
TIE | 17 69 | TIE
TIE | 18 68 | TIE
TIE | 19 67 | TIE
ain<0> | 20 66 | TIE
TIE | 21 XC9572-7-PC84 65 | TIE
VCC | 22 64 | VCC
ain<1> | 23 63 | TIE
ain<2> | 24 62 | TIE
ain<3> | 25 61 | q<3>
bin<0> | 26 60 | GND
GND | 27 59 | TDO
TDI | 28 58 | q<2>
TMS | 29 57 | TIE
TCK | 30 56 | q<0>
bin<1> | 31 55 | TIE
bin<3> | 32 54 | TIE
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
T b T s T V T T T G T T T T T T G T T q T
I i I e I C I I I N I I I I I I N I I < I
E n E l E C E E E D E E E E E E D E E 1 E
< >
2
>
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9572-7-PC84
Use Timing Constraints : ON
Use Design Location Constraints : ON
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : ON
Collapsing pterm limit : 25
Collapsing input limit : 36
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