ex7.tim

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· TIM 代码 · 共 57 行

                           Performance Summary Report
                           --------------------------

Design:     ex7
Device:     XC9572-7-PC84
Speed File: Version 3.0
Program:    Timing Report Generator:  version E.38
Date:       Wed Mar 12 09:00:49 2008

Performance Summary: 

Pad to Pad (tPD)                          :         18.0ns (2 macrocell levels)
Pad 'bin<0>' to Pad 'q<0>'                                        

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From      a     a     a     a     b     b     b     b
 \          i     i     i     i     i     i     i     i
  \         n     n     n     n     n     n     n     n
   \        <     <     <     <     <     <     <     <
    \       0     1     2     3     0     1     2     3
     \      >     >     >     >     >     >     >     >
      \                                                
  To   \------------------------------------------------

q<0>     18.0                    18.0                  
q<1>           18.0                    18.0            
q<2>                 18.0                    18.0      
q<3>                       18.0                    18.0

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU) -             Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and end at register D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.