ex8.out

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

Reading in the Synopsys vhdl primitives.
Warning: Variable 'cqi' is being read 
	in routine EX8 line 18 in file 'D:/temp/eda6000/xc95/ex8/ex8.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)

Inferred memory devices in process 
	in routine EX8 line 18 in file
         'D:/temp/eda6000/xc95/ex8/ex8.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       cqi_reg       | Flip-flop |   4   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================

cqi_reg (width 4)
-----------------
    Async-reset: rst


Writing to hnl file 'd:\temp\EDA6000\XC95\EX8\ex8/workdirs/WORK/EX8.hnl'