ex8.rpt
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RPT
355 行
cpldfit: version E.38 Xilinx Inc.
Fitter Report
Design Name: ex8 Date: 3-12-2008, 9:05AM
Device Used: XC9572-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
5 /72 ( 6%) 13 /360 ( 3%) 4 /72 ( 5%) 8 /69 ( 11%) 10 /144 ( 6%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 3 3 | I/O : 8 55
Output : 1 1 | GCK/IO : 0 3
Bidirectional : 4 4 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 8 8
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 4
Non-registered Macrocell driving I/O 1
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 5 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 5 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
cout 1 4 FB2_1 STD FAST 63 I/O O
outy<0> 3 3 FB4_14 STD FAST 56 I/O I/O
outy<1> 3 4 FB4_4 STD FAST 52 I/O I/O
outy<2> 3 5 FB4_12 STD FAST 58 I/O I/O
outy<3> 3 6 FB4_13 STD FAST 61 I/O I/O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk FB1_18 24 I/O I
ena FB1_16 23 I/O I
rst FB1_13 20 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 0 0 0 0 0/0 18
FB2 1 4 4 1 1/0 17
FB3 0 0 0 0 0/0 17
FB4 4 6 6 12 0/4 17
---- ----- ----- -----
5 13 1/4 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 4 I/O
(unused) 0 0 0 5 FB1_2 1 I/O
(unused) 0 0 0 5 FB1_3 6 I/O
(unused) 0 0 0 5 FB1_4 7 I/O
(unused) 0 0 0 5 FB1_5 2 I/O
(unused) 0 0 0 5 FB1_6 3 I/O
(unused) 0 0 0 5 FB1_7 11 I/O
(unused) 0 0 0 5 FB1_8 5 I/O
(unused) 0 0 0 5 FB1_9 9 GCK/I/O
(unused) 0 0 0 5 FB1_10 13 I/O
(unused) 0 0 0 5 FB1_11 10 GCK/I/O
(unused) 0 0 0 5 FB1_12 18 I/O
(unused) 0 0 0 5 FB1_13 20 I/O I
(unused) 0 0 0 5 FB1_14 12 GCK/I/O
(unused) 0 0 0 5 FB1_15 14 I/O
(unused) 0 0 0 5 FB1_16 23 I/O I
(unused) 0 0 0 5 FB1_17 15 I/O
(unused) 0 0 0 5 FB1_18 24 I/O I
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 4/32
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
cout 1 0 0 4 FB2_1 STD 63 I/O O
(unused) 0 0 0 5 FB2_2 69 I/O
(unused) 0 0 0 5 FB2_3 67 I/O
(unused) 0 0 0 5 FB2_4 68 I/O
(unused) 0 0 0 5 FB2_5 70 I/O
(unused) 0 0 0 5 FB2_6 71 I/O
(unused) 0 0 0 5 FB2_7 76 GTS/I/O
(unused) 0 0 0 5 FB2_8 72 I/O
(unused) 0 0 0 5 FB2_9 74 GSR/I/O
(unused) 0 0 0 5 FB2_10 75 I/O
(unused) 0 0 0 5 FB2_11 77 GTS/I/O
(unused) 0 0 0 5 FB2_12 79 I/O
(unused) 0 0 0 5 FB2_13 80 I/O
(unused) 0 0 0 5 FB2_14 81 I/O
(unused) 0 0 0 5 FB2_15 83 I/O
(unused) 0 0 0 5 FB2_16 82 I/O
(unused) 0 0 0 5 FB2_17 84 I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: "outy<0>".PIN 3: "outy<2>".PIN 4: "outy<3>".PIN
2: "outy<1>".PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
cout XXXX.................................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 25 I/O
(unused) 0 0 0 5 FB3_2 17 I/O
(unused) 0 0 0 5 FB3_3 31 I/O
(unused) 0 0 0 5 FB3_4 32 I/O
(unused) 0 0 0 5 FB3_5 19 I/O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 35 I/O
(unused) 0 0 0 5 FB3_8 21 I/O
(unused) 0 0 0 5 FB3_9 26 I/O
(unused) 0 0 0 5 FB3_10 40 I/O
(unused) 0 0 0 5 FB3_11 33 I/O
(unused) 0 0 0 5 FB3_12 41 I/O
(unused) 0 0 0 5 FB3_13 43 I/O
(unused) 0 0 0 5 FB3_14 36 I/O
(unused) 0 0 0 5 FB3_15 37 I/O
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