ex8.mod

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex8";

/* port names and type */
INPUT S:PIN24 = clk;
INPUT S:PIN23 = ena;
INPUT S:PIN20 = rst;
OUTPUT S:PIN63 = cout;
OUTPUT S:PIN56 = outy<0>;
OUTPUT S:PIN52 = outy<1>;
OUTPUT S:PIN58 = outy<2>;
OUTPUT S:PIN61 = outy<3>;

/* timing arc definitions */
clk_cout_delay: DELAY clk cout;
clk_outy<0>_delay: DELAY clk outy<0>;
clk_outy<1>_delay: DELAY clk outy<1>;
clk_outy<2>_delay: DELAY clk outy<2>;
clk_outy<3>_delay: DELAY clk outy<3>;

/* timing check arc definitions */
ena_clk_setup: SETUP(POSEDGE) ena clk;
ena_clk_hold: HOLD(POSEDGE) ena clk;

ENDMODEL