ex8.gyd

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

Pin Freeze File:  version E.38

957284 XC9572-7-PC84
clk S:PIN24
ena S:PIN23
rst S:PIN20
cout S:PIN63
outy<0> S:PIN56
outy<1> S:PIN52
outy<2> S:PIN58
outy<3> S:PIN61


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.


PARTITION FB2_1 N_cout


PARTITION FB4_4 "N_outy<1>"
PARTITION FB4_12 "N_outy<2>" "N_outy<3>" "N_outy<0>"