ex6.out

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· OUT 代码 · 共 54 行

Reading in the Synopsys vhdl primitives.

Inferred memory devices in process 
	in routine EX6 line 15 in file
         'D:/temp/eda6000/xc95/ex6/ex6.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      reg8_reg       | Flip-flop |   7   |  N  | N  | ?  | ?  | ?  | ?  | ?  |
|      sout_reg       | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
===============================================================================

reg8_reg<4>
-----------
    set/reset/toggle: none


reg8_reg<2>
-----------
    set/reset/toggle: none


reg8_reg<6>
-----------
    set/reset/toggle: none


reg8_reg<3>
-----------
    set/reset/toggle: none


reg8_reg<7>
-----------
    set/reset/toggle: none


reg8_reg<1>
-----------
    set/reset/toggle: none


reg8_reg<5>
-----------
    set/reset/toggle: none


sout_reg
--------
    set/reset/toggle: none


Writing to hnl file 'd:\temp\EDA6000\XC95\EX6\ex6/workdirs/WORK/EX6.hnl'