ex6.mod

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex6";

/* port names and type */
INPUT S:PIN33 = load;
INPUT S:PIN36 = clk;
INPUT S:PIN23 = din<1>;
INPUT S:PIN24 = din<2>;
INPUT S:PIN25 = din<3>;
INPUT S:PIN26 = din<4>;
INPUT S:PIN31 = din<5>;
INPUT S:PIN34 = din<6>;
INPUT S:PIN32 = din<7>;
INPUT S:PIN20 = din<0>;
OUTPUT S:PIN56 = sout;

/* timing arc definitions */
clk_sout_delay: DELAY clk sout;

/* timing check arc definitions */
din<0>_clk_setup: SETUP(POSEDGE) din<0> clk;
din<1>_clk_setup: SETUP(POSEDGE) din<1> clk;
din<2>_clk_setup: SETUP(POSEDGE) din<2> clk;
din<3>_clk_setup: SETUP(POSEDGE) din<3> clk;
din<4>_clk_setup: SETUP(POSEDGE) din<4> clk;
din<5>_clk_setup: SETUP(POSEDGE) din<5> clk;
din<6>_clk_setup: SETUP(POSEDGE) din<6> clk;
din<7>_clk_setup: SETUP(POSEDGE) din<7> clk;
load_clk_setup: SETUP(POSEDGE) load clk;
din<0>_clk_hold: HOLD(POSEDGE) din<0> clk;
din<1>_clk_hold: HOLD(POSEDGE) din<1> clk;
din<2>_clk_hold: HOLD(POSEDGE) din<2> clk;
din<3>_clk_hold: HOLD(POSEDGE) din<3> clk;
din<4>_clk_hold: HOLD(POSEDGE) din<4> clk;
din<5>_clk_hold: HOLD(POSEDGE) din<5> clk;
din<6>_clk_hold: HOLD(POSEDGE) din<6> clk;
din<7>_clk_hold: HOLD(POSEDGE) din<7> clk;
load_clk_hold: HOLD(POSEDGE) load clk;

ENDMODEL