time_sim.edn

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 1,572 行 · 第 1/4 页

              )
            )
            (net reg8_3__D1
              (joined
                (portRef OUT (instanceRef reg8_3__D1_29))
                (portRef IN0 (instanceRef reg8_3__XOR))
              )
            )
            (net (rename N_din_3__ "N_din<3>")
              (joined
                (portRef IN1 (instanceRef reg8_3__D2_PT_0_30))
                (portRef OUT (instanceRef N_din_3___33))
              )
            )
            (net reg8_3__D2_PT_0
              (joined
                (portRef OUT (instanceRef reg8_3__D2_PT_0_30))
                (portRef IN0 (instanceRef reg8_3__D2_32))
              )
            )
            (net reg8_4__FBK
              (joined
                (portRef IN1 (instanceRef reg8_3__D2_PT_1_31))
                (portRef OUT (instanceRef reg8_4__FBK_34))
              )
            )
            (net reg8_3__D2_PT_1
              (joined
                (portRef OUT (instanceRef reg8_3__D2_PT_1_31))
                (portRef IN1 (instanceRef reg8_3__D2_32))
              )
            )
            (net reg8_3__D2
              (joined
                (portRef OUT (instanceRef reg8_3__D2_32))
                (portRef IN1 (instanceRef reg8_3__XOR))
              )
            )
            (net reg8_4__Q
              (joined
                (portRef IN (instanceRef reg8_4__FBK_34))
                (portRef OUT (instanceRef reg8_4__REG))
              )
            )
            (net reg8_4__D
              (joined
                (portRef IN (instanceRef reg8_4__REG))
                (portRef OUT (instanceRef reg8_4__XOR))
              )
            )
            (net reg8_4__CLKF
              (joined
                (portRef CLK (instanceRef reg8_4__REG))
                (portRef OUT (instanceRef reg8_4__CLKF_36))
              )
            )
            (net reg8_4__CLKF_PT_0
              (joined
                (portRef OUT (instanceRef reg8_4__CLKF_PT_0_35))
                (portRef IN0 (instanceRef reg8_4__CLKF_36))
                (portRef IN1 (instanceRef reg8_4__CLKF_36))
              )
            )
            (net reg8_4__D1
              (joined
                (portRef OUT (instanceRef reg8_4__D1_37))
                (portRef IN0 (instanceRef reg8_4__XOR))
              )
            )
            (net (rename N_din_4__ "N_din<4>")
              (joined
                (portRef IN1 (instanceRef reg8_4__D2_PT_0_38))
                (portRef OUT (instanceRef N_din_4___41))
              )
            )
            (net reg8_4__D2_PT_0
              (joined
                (portRef OUT (instanceRef reg8_4__D2_PT_0_38))
                (portRef IN0 (instanceRef reg8_4__D2_40))
              )
            )
            (net reg8_5__FBK
              (joined
                (portRef IN1 (instanceRef reg8_4__D2_PT_1_39))
                (portRef OUT (instanceRef reg8_5__FBK_42))
              )
            )
            (net reg8_4__D2_PT_1
              (joined
                (portRef OUT (instanceRef reg8_4__D2_PT_1_39))
                (portRef IN1 (instanceRef reg8_4__D2_40))
              )
            )
            (net reg8_4__D2
              (joined
                (portRef OUT (instanceRef reg8_4__D2_40))
                (portRef IN1 (instanceRef reg8_4__XOR))
              )
            )
            (net reg8_5__Q
              (joined
                (portRef IN (instanceRef reg8_5__FBK_42))
                (portRef OUT (instanceRef reg8_5__REG))
              )
            )
            (net reg8_5__D
              (joined
                (portRef IN (instanceRef reg8_5__REG))
                (portRef OUT (instanceRef reg8_5__XOR))
              )
            )
            (net reg8_5__CLKF
              (joined
                (portRef CLK (instanceRef reg8_5__REG))
                (portRef OUT (instanceRef reg8_5__CLKF_44))
              )
            )
            (net reg8_5__CLKF_PT_0
              (joined
                (portRef OUT (instanceRef reg8_5__CLKF_PT_0_43))
                (portRef IN0 (instanceRef reg8_5__CLKF_44))
                (portRef IN1 (instanceRef reg8_5__CLKF_44))
              )
            )
            (net reg8_5__D1
              (joined
                (portRef OUT (instanceRef reg8_5__D1_45))
                (portRef IN0 (instanceRef reg8_5__XOR))
              )
            )
            (net (rename N_din_5__ "N_din<5>")
              (joined
                (portRef IN1 (instanceRef reg8_5__D2_PT_0_46))
                (portRef OUT (instanceRef N_din_5___49))
              )
            )
            (net reg8_5__D2_PT_0
              (joined
                (portRef OUT (instanceRef reg8_5__D2_PT_0_46))
                (portRef IN0 (instanceRef reg8_5__D2_48))
              )
            )
            (net reg8_6__FBK
              (joined
                (portRef IN1 (instanceRef reg8_5__D2_PT_1_47))
                (portRef OUT (instanceRef reg8_6__FBK_50))
              )
            )
            (net reg8_5__D2_PT_1
              (joined
                (portRef OUT (instanceRef reg8_5__D2_PT_1_47))
                (portRef IN1 (instanceRef reg8_5__D2_48))
              )
            )
            (net reg8_5__D2
              (joined
                (portRef OUT (instanceRef reg8_5__D2_48))
                (portRef IN1 (instanceRef reg8_5__XOR))
              )
            )
            (net reg8_6__Q
              (joined
                (portRef IN (instanceRef reg8_6__FBK_50))
                (portRef OUT (instanceRef reg8_6__REG))
              )
            )
            (net reg8_6__D
              (joined
                (portRef IN (instanceRef reg8_6__REG))
                (portRef OUT (instanceRef reg8_6__XOR))
              )
            )
            (net reg8_6__CLKF
              (joined
                (portRef CLK (instanceRef reg8_6__REG))
                (portRef OUT (instanceRef reg8_6__CLKF_52))
              )
            )
            (net reg8_6__CLKF_PT_0
              (joined
                (portRef OUT (instanceRef reg8_6__CLKF_PT_0_51))
                (portRef IN0 (instanceRef reg8_6__CLKF_52))
                (portRef IN1 (instanceRef reg8_6__CLKF_52))
              )
            )
            (net reg8_6__D1
              (joined
                (portRef OUT (instanceRef reg8_6__D1_53))
                (portRef IN0 (instanceRef reg8_6__XOR))
              )
            )
            (net (rename N_din_6__ "N_din<6>")
              (joined
                (portRef IN1 (instanceRef reg8_6__D2_PT_0_54))
                (portRef OUT (instanceRef N_din_6___57))
              )
            )
            (net reg8_6__D2_PT_0
              (joined
                (portRef OUT (instanceRef reg8_6__D2_PT_0_54))
                (portRef IN0 (instanceRef reg8_6__D2_56))
              )
            )
            (net reg8_7__FBK
              (joined
                (portRef IN1 (instanceRef reg8_6__D2_PT_1_55))
                (portRef OUT (instanceRef reg8_7__FBK_58))
                (portRef IN1 (instanceRef reg8_7__D2_PT_1_63))
              )
            )
            (net reg8_6__D2_PT_1
              (joined
                (portRef OUT (instanceRef reg8_6__D2_PT_1_55))
                (portRef IN1 (instanceRef reg8_6__D2_56))
              )
            )
            (net reg8_6__D2
              (joined
                (portRef OUT (instanceRef reg8_6__D2_56))
                (portRef IN1 (instanceRef reg8_6__XOR))
              )
            )
            (net reg8_7__Q
              (joined
                (portRef IN (instanceRef reg8_7__FBK_58))
                (portRef OUT (instanceRef reg8_7__REG))
              )
            )
            (net reg8_7__D
              (joined
                (portRef IN (instanceRef reg8_7__REG))
                (portRef OUT (instanceRef reg8_7__XOR))
              )
            )
            (net reg8_7__CLKF
              (joined
                (portRef CLK (instanceRef reg8_7__REG))
                (portRef OUT (instanceRef reg8_7__CLKF_60))
              )
            )
            (net reg8_7__CLKF_PT_0
              (joined
                (portRef OUT (instanceRef reg8_7__CLKF_PT_0_59))
                (portRef IN0 (instanceRef reg8_7__CLKF_60))
                (portRef IN1 (instanceRef reg8_7__CLKF_60))
              )
            )
            (net reg8_7__D1
              (joined
                (portRef OUT (instanceRef reg8_7__D1_61))
                (portRef IN0 (instanceRef reg8_7__XOR))
              )
            )
            (net (rename N_din_7__ "N_din<7>")
              (joined
                (portRef IN1 (instanceRef reg8_7__D2_PT_0_62))
                (portRef OUT (instanceRef N_din_7___65))
              )
            )
            (net reg8_7__D2_PT_0
              (joined
                (portRef OUT (instanceRef reg8_7__D2_PT_0_62))
                (portRef IN0 (instanceRef reg8_7__D2_64))
              )
            )
            (net reg8_7__D2_PT_1
              (joined
                (portRef OUT (instanceRef reg8_7__D2_PT_1_63))
                (portRef IN1 (instanceRef reg8_7__D2_64))
              )
            )
            (net reg8_7__D2
              (joined
                (portRef OUT (instanceRef reg8_7__D2_64))
                (portRef IN1 (instanceRef reg8_7__XOR))
              )
            )
            (net VCC
              (joined
                (portRef CE (instanceRef N_sout_REG))
                (portRef OUT (instanceRef VCC_ONE))
                (portRef CE (instanceRef reg8_1__REG))
                (portRef CE (instanceRef reg8_2__REG))
                (portRef CE (instanceRef reg8_3__REG))
                (portRef CE (instanceRef reg8_4__REG))
                (portRef CE (instanceRef reg8_5__REG))
                (portRef CE (instanceRef reg8_6__REG))
                (portRef CE (instanceRef reg8_7__REG))
              )
            )
            (net GND
              (joined
                (portRef OUT (instanceRef GND_ZERO))
                (portRef IN0 (instanceRef N_sout_D1_4))
                (portRef IN1 (instanceRef N_sout_D1_4))
                (portRef IN0 (instanceRef reg8_1__D1_13))
                (portRef IN1 (instanceRef reg8_1__D1_13))
                (portRef IN0 (instanceRef reg8_2__D1_21))
                (portRef IN1 (instanceRef reg8_2__D1_21))
                (portRef IN0 (instanceRef reg8_3__D1_29))
                (portRef IN1 (instanceRef reg8_3__D1_29))
                (portRef IN0 (instanceRef reg8_4__D1_37))
                (portRef IN1 (instanceRef reg8_4__D1_37))
                (portRef IN0 (instanceRef reg8_5__D1_45))
                (portRef IN1 (instanceRef reg8_5__D1_45))
                (portRef IN0 (instanceRef reg8_6__D1_53))
                (portRef IN1 (instanceRef reg8_6__D1_53))
                (portRef IN0 (instanceRef reg8_7__D1_61))
                (portRef IN1 (instanceRef reg8_7__D1_61))
                (portRef SET (instanceRef N_sout_REG))
                (portRef SET (instanceRef reg8_1__REG))
                (portRef SET (instanceRef reg8_2__REG))
                (portRef SET (instanceRef reg8_3__REG))
                (portRef SET (instanceRef reg8_4__REG))
                (portRef SET (instanceRef reg8_5__REG))
                (portRef SET (instanceRef reg8_6__REG))
                (portRef SET (instanceRef reg8_7__REG))
              )
            )
            (net PRLD
              (joined
                (portRef RST (instanceRef N_sout_REG))
                (portRef RST (instanceRef reg8_1__REG))
                (portRef RST (instanceRef reg8_2__REG))
                (portRef RST (instanceRef reg8_3__REG))
                (portRef RST (instanceRef reg8_4__REG))
                (portRef RST (instanceRef reg8_5__REG))
                (portRef RST (instanceRef reg8_6__REG))
                (portRef RST (instanceRef reg8_7__REG))
              )
              (property INIT (string "0") (owner "Xilinx"))
            )
            (net NlwInverterSignal_N_sout_D2_PT_1_IN0
              (joined
                (portRef OUT (instanceRef NlwInverterBlock_N_sout_D2_PT_1_IN0))
                (portRef IN0 (instanceRef N_sout_D2_PT_1_6))
              )
            )
            (net NlwInverterSignal_reg8_1__D2_PT_1_IN0
              (joined
                (portRef OUT (instanceRef NlwInverterBlock_reg8_1__D2_PT_1_IN0))
                (portRef IN0 (instanceRef reg8_1__D2_PT_1_15))
              )
            )
            (net NlwInverterSignal_reg8_2__D2_PT_1_IN0
              (joined
                (portRef OUT (instanceRef NlwInverterBlock_reg8_2__D2_PT_1_IN0))
                (portRef IN0 (instanceRef reg8_2__D2_PT_1_23))
              )
            )
            (net NlwInverterSignal_reg8_3__D2_PT_1_IN0
              (joined
                (portRef OUT (instanceRef NlwInverterBlock_reg8_3__D2_PT_1_IN0))
                (portRef IN0 (instanceRef reg8_3__D2_PT_1_31))
              )
            )
            (net NlwInverterSignal_reg8_4__D2_PT_1_IN0
              (joined
                (portRef OUT (instanceRef NlwInverterBlock_reg8_4__D2_PT_1_IN0))
                (portRef IN0 (instanceRef reg8_4__D2_PT_1_39))
              )
            )
            (net NlwInverterSignal_reg8_5__D2_PT_1_IN0
              (joined
                (portRef OUT (instanceRef NlwInverterBlock_reg8_5__D2_PT_1_IN0))
                (portRef IN0 (instanceRef reg8_5__D2_PT_1_47))
              )
            )
            (net NlwInverterSignal_reg8_6__D2_PT_1_IN0
              (joined
                (portRef OUT (instanceRef NlwInverterBlock_reg8_6__D2_PT_1_IN0))
                (portRef IN0 (instanceRef reg8_6__D2_PT_1_55))
              )
            )
            (net NlwInverterSignal_reg8_7__D2_PT_1_IN0
              (joined
                (portRef OUT (instanceRef NlwInverterBlock_reg8_7__D2_PT_1_IN0))
                (portRef IN0 (instanceRef reg8_7__D2_PT_1_63))
              )
            )
          )
      )
    )
  )

  (design ex6
    (cellRef ex6
      (libraryRef ex6_lib)
    )
  )
)