ex6.tim

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                           Performance Summary Report
                           --------------------------

Design:     ex6
Device:     XC95108-7-PC84
Speed File: Version 3.0
Program:    Timing Report Generator:  version E.38
Date:       Wed Mar 12 08:55:00 2008

Performance Summary: 

Clock net 'clk' path delays:

Clock Pad to Output Pad (tCO)             :          8.5ns (1 macrocell levels)
Clock Pad 'clk' to Output Pad 'sout'                              (Pterm Clock)

Clock to Setup (tCYC)                     :          8.0ns (1 macrocell levels)
Clock to Q, net 'reg8<2>.Q' to DFF Setup(D) at 'reg8<1>.D'        (Pterm Clock)

Setup to Clock at the Pad (tSU)           :          0.5ns (0 macrocell levels)
Data signal 'load' to DFF D input Pin at 'reg8<1>.D'
Clock pad 'clk'                                                   (Pterm Clock)

                          Minimum Clock Period: 10.0ns
                     Maximum Internal Clock Speed: 100.0Mhz
                         (Limited by Clock Pulse Width)

--------------------------------------------------------------------------------
                      Clock Pad to Output Pad (tCO) (nsec)

\ From      c
 \          l
  \         k
   \         
    \        
     \       
      \      
  To   \------

sout      8.5

--------------------------------------------------------------------------------
                       Setup to Clock at Pad (tSU) (nsec)

\ From      c
 \          l
  \         k
   \         
    \        
     \       
      \      
  To   \------

din<0>    0.5
din<1>    0.5
din<2>    0.5
din<3>    0.5
din<4>    0.5
din<5>    0.5
din<6>    0.5
din<7>    0.5
load      0.5

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                  (Clock: clk)

\ From        r     r     r     r     r     r     r
 \            e     e     e     e     e     e     e
  \           g     g     g     g     g     g     g
   \          8     8     8     8     8     8     8
    \         <     <     <     <     <     <     <
     \        1     2     3     4     5     6     7
      \       >     >     >     >     >     >     >
       \      .     .     .     .     .     .     .
        \     Q     Q     Q     Q     Q     Q     Q
  To     \------------------------------------------

reg8<1>.D         8.0                              
reg8<2>.D               8.0                        
reg8<3>.D                     8.0                  
reg8<4>.D                           8.0            
reg8<5>.D                                 8.0      
reg8<6>.D                                       8.0
reg8<7>.D                                       8.0
sout.D      8.0                                    

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU) -             Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and end at register D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.