ex6.rpt
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 377 行 · 第 1/2 页
RPT
377 行
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 17/19
Number of signals used by logic mapping into function block: 17
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 46 I/O
(unused) 0 0 0 5 FB4_2 44 I/O
(unused) 0 0 0 5 FB4_3 51 I/O
(unused) 0 0 0 5 FB4_4 52 I/O
(unused) 0 0 0 5 FB4_5 47 I/O
(unused) 0 0 0 5 FB4_6 54 I/O
(unused) 0 0 0 5 FB4_7 55 I/O
(unused) 0 0 0 5 FB4_8 48 I/O
(unused) 0 0 0 5 FB4_9 50 I/O
(unused) 0 0 0 5 FB4_10 57 I/O
reg8<7> 3 0 0 2 FB4_11 STD 53 I/O (b)
reg8<6> 3 0 0 2 FB4_12 STD 58 I/O (b)
reg8<5> 3 0 0 2 FB4_13 STD 61 I/O (b)
sout 3 0 0 2 FB4_14 STD 56 I/O O
reg8<4> 3 0 0 2 FB4_15 STD 65 I/O (b)
reg8<3> 3 0 0 2 FB4_16 STD 62 I/O (b)
reg8<2> 3 0 0 2 FB4_17 STD 66 I/O (b)
reg8<1> 3 0 0 2 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: clk 7: "din<5>" 13: "reg8<3>.FBK".LFBK
2: "din<0>" 8: "din<6>" 14: "reg8<4>.FBK".LFBK
3: "din<1>" 9: "din<7>" 15: "reg8<5>.FBK".LFBK
4: "din<2>" 10: load 16: "reg8<6>.FBK".LFBK
5: "din<3>" 11: "reg8<1>.FBK".LFBK
17: "reg8<7>.FBK".LFBK
6: "din<4>" 12: "reg8<2>.FBK".LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
reg8<7> X.......XX......X....................... 4 4
reg8<6> X......X.X......X....................... 4 4
reg8<5> X.....X..X.....X........................ 4 4
sout XX.......XX............................. 4 4
reg8<4> X....X...X....X......................... 4 4
reg8<3> X...X....X...X.......................... 4 4
reg8<2> X..X.....X..X........................... 4 4
reg8<1> X.X......X.X............................ 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
sout := load * "din<0>"
+ /load * "reg8<1>.FBK".LFBK
sout.CLKF = clk
sout.PRLD = GND
"reg8<1>" := load * "din<1>"
+ /load * "reg8<2>.FBK".LFBK
"reg8<1>".CLKF = clk
"reg8<1>".PRLD = GND
"reg8<2>" := load * "din<2>"
+ /load * "reg8<3>.FBK".LFBK
"reg8<2>".CLKF = clk
"reg8<2>".PRLD = GND
"reg8<3>" := load * "din<3>"
+ /load * "reg8<4>.FBK".LFBK
"reg8<3>".CLKF = clk
"reg8<3>".PRLD = GND
"reg8<4>" := load * "din<4>"
+ /load * "reg8<5>.FBK".LFBK
"reg8<4>".CLKF = clk
"reg8<4>".PRLD = GND
"reg8<5>" := load * "din<5>"
+ /load * "reg8<6>.FBK".LFBK
"reg8<5>".CLKF = clk
"reg8<5>".PRLD = GND
"reg8<6>" := load * "din<6>"
+ /load * "reg8<7>.FBK".LFBK
"reg8<6>".CLKF = clk
"reg8<6>".PRLD = GND
"reg8<7>" := load * "din<7>"
+ /load * "reg8<7>.FBK".LFBK
"reg8<7>".CLKF = clk
"reg8<7>".PRLD = GND
**************************** Device Pin Out ****************************
Device : XC9572-7-PC84
T T T G T T T T T T T T T T T T T V T T T
I I I N I I I I I I I I I I I I I C I I I
E E E D E E E E E E E E E E E E E C E E E
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
TIE | 12 74 | TIE
TIE | 13 73 | VCC
TIE | 14 72 | TIE
TIE | 15 71 | TIE
GND | 16 70 | TIE
TIE | 17 69 | TIE
TIE | 18 68 | TIE
TIE | 19 67 | TIE
din<0> | 20 66 | TIE
TIE | 21 XC9572-7-PC84 65 | TIE
VCC | 22 64 | VCC
din<1> | 23 63 | TIE
din<2> | 24 62 | TIE
din<3> | 25 61 | TIE
din<4> | 26 60 | GND
GND | 27 59 | TDO
TDI | 28 58 | TIE
TMS | 29 57 | TIE
TCK | 30 56 | sout
din<5> | 31 55 | TIE
din<7> | 32 54 | TIE
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
l d T c T V T T T G T T T T T T G T T T T
o i I l I C I I I N I I I I I I N I I I I
a n E k E C E E E D E E E E E E D E E E E
d <
6
>
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9572-7-PC84
Use Timing Constraints : ON
Use Design Location Constraints : ON
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : ON
Collapsing pterm limit : 25
Collapsing input limit : 36
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