ex6.vm6

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· VM6 代码 · 共 454 行 · 第 1/2 页

VM6
454 行
字号
12
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 519 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | reg8<6>.FBK | 591 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<6>.Q | reg8<6> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | reg8<5> | 524 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<5>.Q | reg8<5> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | reg8<5>.FBK | 590 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<5>.Q | reg8<5> | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | reg8<5>.SI | reg8<5> | 0 | 4 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_load | 518 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_load | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_din<5> | 534 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_din<5> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 519 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | reg8<6>.FBK | 591 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<6>.Q | reg8<6> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | reg8<5>.D1 | 568 | ? | 0 | 4096 | reg8<5> | NULL | NULL | reg8<5>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | reg8<5>.D2 | 569 | ? | 0 | 4096 | reg8<5> | NULL | NULL | reg8<5>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 2 | IV_TRUE | N_load | IV_TRUE | N_din<5>
SPPTERM | 2 | IV_FALSE | N_load | IV_TRUE | reg8<6>.FBK
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | reg8<5>.CLKF | 570 | ? | 0 | 4096 | reg8<5> | NULL | NULL | reg8<5>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk

SRFF_INSTANCE | reg8<5>.REG | reg8<5> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | reg8<5>.D | 567 | ? | 0 | 0 | reg8<5> | NULL | NULL | reg8<5>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | reg8<5>.CLKF | 570 | ? | 0 | 4096 | reg8<5> | NULL | NULL | reg8<5>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | reg8<5>.Q | 571 | ? | 0 | 0 | reg8<5> | NULL | NULL | reg8<5>.REG | 0 | 8 | SRFF_Q

INPUT_INSTANCE | 0 | 0 | NULL | N_din<6> | EX6_COPY_0_COPY_0 | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 5 | II_IN
NODE | din<6> | 542 | PI | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
NODE | N_din<6> | 530 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_din<6> | 0 | 5 | II_IMUX

MACROCELL_INSTANCE | PrldLow+OptxMapped+ClkInv | reg8<6> | EX6_COPY_0_COPY_0 | 2222982144 | 4 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_load | 518 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_load | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_din<6> | 530 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_din<6> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 519 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | reg8<7>.FBK | 592 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<7>.Q | reg8<7> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | reg8<6> | 525 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<6>.Q | reg8<6> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | reg8<6>.FBK | 591 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<6>.Q | reg8<6> | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | reg8<6>.SI | reg8<6> | 0 | 4 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_load | 518 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_load | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_din<6> | 530 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_din<6> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 519 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | reg8<7>.FBK | 592 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<7>.Q | reg8<7> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | reg8<6>.D1 | 573 | ? | 0 | 4096 | reg8<6> | NULL | NULL | reg8<6>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | reg8<6>.D2 | 574 | ? | 0 | 4096 | reg8<6> | NULL | NULL | reg8<6>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 2 | IV_TRUE | N_load | IV_TRUE | N_din<6>
SPPTERM | 2 | IV_FALSE | N_load | IV_TRUE | reg8<7>.FBK
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | reg8<6>.CLKF | 575 | ? | 0 | 4096 | reg8<6> | NULL | NULL | reg8<6>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk

SRFF_INSTANCE | reg8<6>.REG | reg8<6> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | reg8<6>.D | 572 | ? | 0 | 0 | reg8<6> | NULL | NULL | reg8<6>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | reg8<6>.CLKF | 575 | ? | 0 | 4096 | reg8<6> | NULL | NULL | reg8<6>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | reg8<6>.Q | 576 | ? | 0 | 0 | reg8<6> | NULL | NULL | reg8<6>.REG | 0 | 8 | SRFF_Q

INPUT_INSTANCE | 0 | 0 | NULL | N_din<7> | EX6_COPY_0_COPY_0 | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 5 | II_IN
NODE | din<7> | 544 | PI | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
NODE | N_din<7> | 532 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_din<7> | 0 | 5 | II_IMUX

MACROCELL_INSTANCE | PrldLow+OptxMapped+ClkInv | reg8<7> | EX6_COPY_0_COPY_0 | 2222982144 | 4 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_load | 518 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_load | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_din<7> | 532 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_din<7> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 519 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | reg8<7>.FBK | 592 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<7>.Q | reg8<7> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | reg8<7> | 526 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<7>.Q | reg8<7> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | reg8<7>.FBK | 592 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<7>.Q | reg8<7> | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | reg8<7>.SI | reg8<7> | 0 | 4 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_load | 518 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_load | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_din<7> | 532 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_din<7> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 519 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | reg8<7>.FBK | 592 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<7>.Q | reg8<7> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | reg8<7>.D1 | 578 | ? | 0 | 4096 | reg8<7> | NULL | NULL | reg8<7>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | reg8<7>.D2 | 579 | ? | 0 | 4096 | reg8<7> | NULL | NULL | reg8<7>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 2 | IV_TRUE | N_load | IV_TRUE | N_din<7>
SPPTERM | 2 | IV_FALSE | N_load | IV_TRUE | reg8<7>.FBK
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | reg8<7>.CLKF | 580 | ? | 0 | 4096 | reg8<7> | NULL | NULL | reg8<7>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk

SRFF_INSTANCE | reg8<7>.REG | reg8<7> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | reg8<7>.D | 577 | ? | 0 | 0 | reg8<7> | NULL | NULL | reg8<7>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | reg8<7>.CLKF | 580 | ? | 0 | 4096 | reg8<7> | NULL | NULL | reg8<7>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | reg8<7>.Q | 581 | ? | 0 | 0 | reg8<7> | NULL | NULL | reg8<7>.REG | 0 | 8 | SRFF_Q

INPUT_INSTANCE | 0 | 0 | NULL | N_din<0> | EX6_COPY_0_COPY_0 | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 5 | II_IN
NODE | din<0> | 541 | PI | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
NODE | N_din<0> | 529 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_din<0> | 0 | 5 | II_IMUX

MACROCELL_INSTANCE | PrldLow+OptxMapped | N_sout | EX6_COPY_0_COPY_0 | 2155873280 | 4 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_load | 518 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_load | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_din<0> | 529 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_din<0> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 519 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | reg8<1>.FBK | 593 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<1>.Q | reg8<1> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | N_sout | 535 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | N_sout.Q | N_sout | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | N_sout.UIM | 594 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | N_sout.Q | N_sout | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | N_sout.SI | N_sout | 0 | 4 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_load | 518 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_load | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_din<0> | 529 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_din<0> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 519 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | reg8<1>.FBK | 593 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | reg8<1>.Q | reg8<1> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | N_sout.D1 | 583 | ? | 0 | 4096 | N_sout | NULL | NULL | N_sout.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | N_sout.D2 | 584 | ? | 0 | 4096 | N_sout | NULL | NULL | N_sout.SI | 2 | 9 | MC_SI_D2
SPPTERM | 2 | IV_TRUE | N_load | IV_TRUE | N_din<0>
SPPTERM | 2 | IV_FALSE | N_load | IV_TRUE | reg8<1>.FBK
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | N_sout.CLKF | 585 | ? | 0 | 4096 | N_sout | NULL | NULL | N_sout.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk

SRFF_INSTANCE | N_sout.REG | N_sout | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | N_sout.D | 582 | ? | 0 | 0 | N_sout | NULL | NULL | N_sout.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | N_sout.CLKF | 585 | ? | 0 | 4096 | N_sout | NULL | NULL | N_sout.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | N_sout.Q | 586 | ? | 0 | 0 | N_sout | NULL | NULL | N_sout.REG | 0 | 8 | SRFF_Q

OUTPUT_INSTANCE | 0 | sout | EX6_COPY_0_COPY_0 | 3 | 1 | 1
INPUT_NODE_TYPE | 0 | 6 | OI_IN
NODE | N_sout | 535 | ? | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | N_sout.Q | N_sout | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
NODE | sout | 536 | PO | 0 | 0 | EX6_COPY_0_COPY_0 | NULL | NULL | sout | 0 | 6 | OI_OUT

FB_INSTANCE | FOOBAR1_ | EX6_COPY_0_COPY_0 | 0 | 0 | 0
FBPIN | 13 | NULL | 0 | N_din<0> | 0 | NULL | 0 | 20 | 49152
FBPIN | 16 | NULL | 0 | N_din<1> | 0 | NULL | 0 | 23 | 49152
FBPIN | 18 | NULL | 0 | N_din<2> | 0 | NULL | 0 | 24 | 49152

FB_INSTANCE | FOOBAR2_ | EX6_COPY_0_COPY_0 | 0 | 0 | 0

FB_INSTANCE | FOOBAR3_ | EX6_COPY_0_COPY_0 | 0 | 0 | 0
FBPIN | 1 | NULL | 0 | N_din<3> | 0 | NULL | 0 | 25 | 49152
FBPIN | 3 | NULL | 0 | N_din<5> | 0 | NULL | 0 | 31 | 49152
FBPIN | 4 | NULL | 0 | N_din<7> | 0 | NULL | 0 | 32 | 49152
FBPIN | 6 | NULL | 0 | N_din<6> | 0 | NULL | 0 | 34 | 49152
FBPIN | 9 | NULL | 0 | N_din<4> | 0 | NULL | 0 | 26 | 49152
FBPIN | 11 | NULL | 0 | N_load | 0 | NULL | 0 | 33 | 49152
FBPIN | 14 | NULL | 0 | N_clk | 0 | NULL | 0 | 36 | 49152

FB_INSTANCE | FOOBAR4_ | EX6_COPY_0_COPY_0 | 0 | 0 | 0
FBPIN | 11 | reg8<7> | 1 | NULL | 0 | NULL | 0 | 53 | 49152
FBPIN | 12 | reg8<6> | 1 | NULL | 0 | NULL | 0 | 58 | 49152
FBPIN | 13 | reg8<5> | 1 | NULL | 0 | NULL | 0 | 61 | 49152
FBPIN | 14 | N_sout | 1 | NULL | 0 | sout | 1 | 56 | 49152
FBPIN | 15 | reg8<4> | 1 | NULL | 0 | NULL | 0 | 65 | 49152
FBPIN | 16 | reg8<3> | 1 | NULL | 0 | NULL | 0 | 62 | 49152
FBPIN | 17 | reg8<2> | 1 | NULL | 0 | NULL | 0 | 66 | 49152
FBPIN | 18 | reg8<1> | 1 | NULL | 0 | NULL | 0

FB_INSTANCE | INPUTPINS_FOOBAR5_ | EX6_COPY_0_COPY_0 | 0 | 0 | 0

FB_ORDER_OF_INPUTS | FOOBAR4_ | 4 | din<6> | 34 | 6 | din<1> | 23 | 10 | reg8<7>.FBK | NULL | 11 | reg8<6>.FBK | NULL | 12 | reg8<5>.FBK | NULL
FB_ORDER_OF_INPUTS | FOOBAR4_ | 14 | reg8<4>.FBK | NULL | 15 | reg8<3>.FBK | NULL | 16 | reg8<2>.FBK | NULL | 17 | reg8<1>.FBK | NULL | 20 | din<7> | 32
FB_ORDER_OF_INPUTS | FOOBAR4_ | 22 | din<3> | 25 | 24 | clk | 36 | 25 | din<2> | 24 | 32 | din<5> | 31 | 33 | load | 33
FB_ORDER_OF_INPUTS | FOOBAR4_ | 34 | din<4> | 26 | 35 | din<0> | 20

FB_IMUX_INDEX | FOOBAR4_ | -1 | -1 | -1 | -1 | 130 | -1 | 132 | -1 | -1 | -1 | 10 | 11 | 12 | -1 | 14 | 15 | 16 | 17 | -1 | -1 | 110 | -1 | 138 | -1 | 104 | 140 | -1 | -1 | -1 | -1 | -1 | -1 | 122 | 86 | 87 | 123
12

ex6.vm6 - 源码说明

本页面展示了「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][」中的 ex6.vm6 源码文件，采用 VM6 编程语言编写，共 454 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

虫虫开发者社区收录了大量与VHDL相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?