ex6.mfd

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

MDF Database:  version 1.0
MDF_INFO | ex6 | XC9572-7-PC84
MACROCELL | 3 | 17 | reg8<1>
ATTRIBUTES | 8586016 | 0
OUTPUTMC | 1 | 3 | 13
INPUTS | 4 | load  | din<1>  | clk  | reg8<2>.FBK".LFBK
INPUTMC | 1 | 3 | 16
INPUTP | 3 | 46 | 35 | 49
EQ | 4 | 
    "reg8<1>"  :=  load * "din<1>"
	+ /load * "reg8<2>.FBK".LFBK
    "reg8<1>".CLKF  =  clk
    "reg8<1>".PRLD  =  GND

MACROCELL | 3 | 16 | reg8<2>
ATTRIBUTES | 8586016 | 0
OUTPUTMC | 1 | 3 | 17
INPUTS | 4 | load  | din<2>  | clk  | reg8<3>.FBK".LFBK
INPUTMC | 1 | 3 | 15
INPUTP | 3 | 46 | 36 | 49
EQ | 4 | 
    "reg8<2>"  :=  load * "din<2>"
	+ /load * "reg8<3>.FBK".LFBK
    "reg8<2>".CLKF  =  clk
    "reg8<2>".PRLD  =  GND

MACROCELL | 3 | 15 | reg8<3>
ATTRIBUTES | 8586016 | 0
OUTPUTMC | 1 | 3 | 16
INPUTS | 4 | load  | din<3>  | clk  | reg8<4>.FBK".LFBK
INPUTMC | 1 | 3 | 14
INPUTP | 3 | 46 | 37 | 49
EQ | 4 | 
    "reg8<3>"  :=  load * "din<3>"
	+ /load * "reg8<4>.FBK".LFBK
    "reg8<3>".CLKF  =  clk
    "reg8<3>".PRLD  =  GND

MACROCELL | 3 | 14 | reg8<4>
ATTRIBUTES | 8586016 | 0
OUTPUTMC | 1 | 3 | 15
INPUTS | 4 | load  | din<4>  | clk  | reg8<5>.FBK".LFBK
INPUTMC | 1 | 3 | 12
INPUTP | 3 | 46 | 38 | 49
EQ | 4 | 
    "reg8<4>"  :=  load * "din<4>"
	+ /load * "reg8<5>.FBK".LFBK
    "reg8<4>".CLKF  =  clk
    "reg8<4>".PRLD  =  GND

MACROCELL | 3 | 12 | reg8<5>
ATTRIBUTES | 8586016 | 0
OUTPUTMC | 1 | 3 | 14
INPUTS | 4 | load  | din<5>  | clk  | reg8<6>.FBK".LFBK
INPUTMC | 1 | 3 | 11
INPUTP | 3 | 46 | 43 | 49
EQ | 4 | 
    "reg8<5>"  :=  load * "din<5>"
	+ /load * "reg8<6>.FBK".LFBK
    "reg8<5>".CLKF  =  clk
    "reg8<5>".PRLD  =  GND

MACROCELL | 3 | 11 | reg8<6>
ATTRIBUTES | 8586016 | 0
OUTPUTMC | 1 | 3 | 12
INPUTS | 4 | load  | din<6>  | clk  | reg8<7>.FBK".LFBK
INPUTMC | 1 | 3 | 10
INPUTP | 3 | 46 | 47 | 49
EQ | 4 | 
    "reg8<6>"  :=  load * "din<6>"
	+ /load * "reg8<7>.FBK".LFBK
    "reg8<6>".CLKF  =  clk
    "reg8<6>".PRLD  =  GND

MACROCELL | 3 | 10 | reg8<7>
ATTRIBUTES | 8586016 | 0
OUTPUTMC | 2 | 3 | 11 | 3 | 10
INPUTS | 4 | load  | din<7>  | clk  | reg8<7>.FBK".LFBK
INPUTMC | 1 | 3 | 10
INPUTP | 3 | 46 | 44 | 49
EQ | 4 | 
    "reg8<7>"  :=  load * "din<7>"
	+ /load * "reg8<7>.FBK".LFBK
    "reg8<7>".CLKF  =  clk
    "reg8<7>".PRLD  =  GND

MACROCELL | 3 | 13 | N_sout
ATTRIBUTES | 8782626 | 0
INPUTS | 4 | load  | din<0>  | clk  | reg8<1>.FBK".LFBK
INPUTMC | 1 | 3 | 17
INPUTP | 3 | 46 | 32 | 49
EQ | 4 | 
    sout  :=  load * "din<0>"
	+ /load * "reg8<1>.FBK".LFBK
    sout.CLKF  =  clk
    sout.PRLD  =  GND

PIN | load | 64 | 0 | N/A | 46 | 8 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 3 | 12 | 3 | 11 | 3 | 10 | 3 | 13
PIN | clk | 64 | 0 | N/A | 49 | 8 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 3 | 12 | 3 | 11 | 3 | 10 | 3 | 13
PIN | din<1> | 64 | 0 | N/A | 35 | 1 | 3 | 17
PIN | din<2> | 64 | 0 | N/A | 36 | 1 | 3 | 16
PIN | din<3> | 64 | 0 | N/A | 37 | 1 | 3 | 15
PIN | din<4> | 64 | 0 | N/A | 38 | 1 | 3 | 14
PIN | din<5> | 64 | 0 | N/A | 43 | 1 | 3 | 12
PIN | din<6> | 64 | 0 | N/A | 47 | 1 | 3 | 11
PIN | din<7> | 64 | 0 | N/A | 44 | 1 | 3 | 10
PIN | din<0> | 64 | 0 | N/A | 32 | 1 | 3 | 13
PIN | sout | 536871040 | 0 | N/A | 71