ex6.gyd

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

Pin Freeze File:  version E.38

9510884 XC95108-7-PC84
clk S:PIN36
din<0> S:PIN20
din<1> S:PIN23
din<2> S:PIN24
din<3> S:PIN25
din<4> S:PIN26
din<5> S:PIN31
din<6> S:PIN34
din<7> S:PIN32
load S:PIN33
sout S:PIN56


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.






PARTITION FB6_11 "reg8<7>" "reg8<6>" "reg8<5>" "reg8<4>"
		 "reg8<3>" "reg8<2>" N_sout "reg8<1>"