ex24.mod

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex24";

/* port names and type */
INPUT S:PIN10 = clk;
INPUT S:PIN4 = rst;
INPUT S:PIN18 = eoc;
INPUT S:PIN36 = din<0>;
INPUT S:PIN33 = din<1>;
INPUT S:PIN35 = din<2>;
INPUT S:PIN37 = din<3>;
INPUT S:PIN40 = din<4>;
INPUT S:PIN39 = din<5>;
INPUT S:PIN41 = din<6>;
INPUT S:PIN43 = din<7>;
INPUT S:PIN82 = datai;
INPUT S:PIN84 = clki;
INPUT S:PIN2 = load;
INPUT S:PIN83 = clko;
TRIOUT S:PIN66 = mem_d<0>;
TRIOUT S:PIN69 = mem_d<1>;
TRIOUT S:PIN68 = mem_d<2>;
TRIOUT S:PIN71 = mem_d<3>;
TRIOUT S:PIN70 = mem_d<4>;
TRIOUT S:PIN72 = mem_d<5>;
TRIOUT S:PIN76 = mem_d<6>;
TRIOUT S:PIN77 = mem_d<7>;
OUTPUT S:PIN19 = start;
OUTPUT S:PIN3 = mem_f;
OUTPUT S:PIN15 = oe;
OUTPUT S:PIN81 = datao;
OUTPUT S:PIN62 = mem_a<13>;
OUTPUT S:PIN63 = mem_a<12>;
OUTPUT S:PIN61 = mem_a<11>;
OUTPUT S:PIN58 = mem_a<10>;
OUTPUT S:PIN52 = mem_a<9>;
OUTPUT S:PIN56 = mem_a<8>;
OUTPUT S:PIN57 = mem_a<7>;
OUTPUT S:PIN55 = mem_a<6>;
OUTPUT S:PIN65 = mem_a<14>;
OUTPUT S:PIN53 = mem_a<5>;
OUTPUT S:PIN51 = mem_a<4>;
OUTPUT S:PIN48 = mem_a<3>;
OUTPUT S:PIN47 = mem_a<2>;
OUTPUT S:PIN46 = mem_a<1>;
OUTPUT S:PIN45 = mem_a<0>;
OUTPUT S:PIN79 = mem_wr;
OUTPUT S:PIN80 = mem_rd;
OUTPUT S:PIN21 = clock;

/* timing arc definitions */
clk_clock_delay: DELAY clk clock;
rst_mem_a<0>_delay: DELAY rst mem_a<0>;
rst_mem_a<10>_delay: DELAY rst mem_a<10>;
rst_mem_a<11>_delay: DELAY rst mem_a<11>;
rst_mem_a<12>_delay: DELAY rst mem_a<12>;
rst_mem_a<13>_delay: DELAY rst mem_a<13>;
rst_mem_a<14>_delay: DELAY rst mem_a<14>;
rst_mem_a<1>_delay: DELAY rst mem_a<1>;
rst_mem_a<2>_delay: DELAY rst mem_a<2>;
rst_mem_a<3>_delay: DELAY rst mem_a<3>;
rst_mem_a<4>_delay: DELAY rst mem_a<4>;
rst_mem_a<5>_delay: DELAY rst mem_a<5>;
rst_mem_a<6>_delay: DELAY rst mem_a<6>;
rst_mem_a<7>_delay: DELAY rst mem_a<7>;
rst_mem_a<8>_delay: DELAY rst mem_a<8>;
rst_mem_a<9>_delay: DELAY rst mem_a<9>;
din<0>_mem_d<0>_delay: DELAY (ENABLE_HIGH) din<0> mem_d<0>;
rst_mem_d<0>_delay: DELAY (ENABLE_HIGH) rst mem_d<0>;
din<1>_mem_d<1>_delay: DELAY (ENABLE_HIGH) din<1> mem_d<1>;
rst_mem_d<1>_delay: DELAY (ENABLE_HIGH) rst mem_d<1>;
rst_mem_d<2>_delay: DELAY (ENABLE_HIGH) rst mem_d<2>;
din<2>_mem_d<2>_delay: DELAY (ENABLE_HIGH) din<2> mem_d<2>;
rst_mem_d<3>_delay: DELAY (ENABLE_HIGH) rst mem_d<3>;
din<3>_mem_d<3>_delay: DELAY (ENABLE_HIGH) din<3> mem_d<3>;
din<4>_mem_d<4>_delay: DELAY (ENABLE_HIGH) din<4> mem_d<4>;
rst_mem_d<4>_delay: DELAY (ENABLE_HIGH) rst mem_d<4>;
din<5>_mem_d<5>_delay: DELAY (ENABLE_HIGH) din<5> mem_d<5>;
rst_mem_d<5>_delay: DELAY (ENABLE_HIGH) rst mem_d<5>;
rst_mem_d<6>_delay: DELAY (ENABLE_HIGH) rst mem_d<6>;
din<6>_mem_d<6>_delay: DELAY (ENABLE_HIGH) din<6> mem_d<6>;
rst_mem_d<7>_delay: DELAY (ENABLE_HIGH) rst mem_d<7>;
din<7>_mem_d<7>_delay: DELAY (ENABLE_HIGH) din<7> mem_d<7>;
rst_mem_rd_delay: DELAY rst mem_rd;
rst_mem_wr_delay: DELAY rst mem_wr;
clko_datao_delay: DELAY clko datao;
clki_mem_a<13>_delay: DELAY clki mem_a<13>;
clki_mem_a<12>_delay: DELAY clki mem_a<12>;
clki_mem_a<11>_delay: DELAY clki mem_a<11>;
clki_mem_a<10>_delay: DELAY clki mem_a<10>;
clki_mem_a<9>_delay: DELAY clki mem_a<9>;
clki_mem_a<8>_delay: DELAY clki mem_a<8>;
clki_mem_a<7>_delay: DELAY clki mem_a<7>;
clki_mem_a<6>_delay: DELAY clki mem_a<6>;
clki_mem_a<14>_delay: DELAY clki mem_a<14>;
clki_mem_a<5>_delay: DELAY clki mem_a<5>;
clki_mem_a<4>_delay: DELAY clki mem_a<4>;
clki_mem_a<3>_delay: DELAY clki mem_a<3>;
clki_mem_a<2>_delay: DELAY clki mem_a<2>;
clki_mem_a<1>_delay: DELAY clki mem_a<1>;
clki_mem_a<0>_delay: DELAY clki mem_a<0>;
clk_mem_d<0>_delay: DELAY (ENABLE_HIGH) clk mem_d<0>;
clk_mem_d<1>_delay: DELAY (ENABLE_HIGH) clk mem_d<1>;
clk_mem_d<2>_delay: DELAY (ENABLE_HIGH) clk mem_d<2>;
clk_mem_d<3>_delay: DELAY (ENABLE_HIGH) clk mem_d<3>;
clk_mem_d<4>_delay: DELAY (ENABLE_HIGH) clk mem_d<4>;
clk_mem_d<5>_delay: DELAY (ENABLE_HIGH) clk mem_d<5>;
clk_mem_d<6>_delay: DELAY (ENABLE_HIGH) clk mem_d<6>;
clk_mem_d<7>_delay: DELAY (ENABLE_HIGH) clk mem_d<7>;
clk_start_delay: DELAY clk start;
clk_mem_f_delay: DELAY clk mem_f;
clk_oe_delay: DELAY clk oe;
clk_mem_a<13>_delay: DELAY clk mem_a<13>;
clk_mem_a<12>_delay: DELAY clk mem_a<12>;
clk_mem_a<11>_delay: DELAY clk mem_a<11>;
clk_mem_a<10>_delay: DELAY clk mem_a<10>;
clk_mem_a<9>_delay: DELAY clk mem_a<9>;
clk_mem_a<8>_delay: DELAY clk mem_a<8>;
clk_mem_a<7>_delay: DELAY clk mem_a<7>;
clk_mem_a<6>_delay: DELAY clk mem_a<6>;
clk_mem_a<14>_delay: DELAY clk mem_a<14>;
clk_mem_a<5>_delay: DELAY clk mem_a<5>;
clk_mem_a<4>_delay: DELAY clk mem_a<4>;
clk_mem_a<3>_delay: DELAY clk mem_a<3>;
clk_mem_a<2>_delay: DELAY clk mem_a<2>;
clk_mem_a<1>_delay: DELAY clk mem_a<1>;
clk_mem_a<0>_delay: DELAY clk mem_a<0>;
clk_mem_wr_delay: DELAY clk mem_wr;

/* timing check arc definitions */
load_clko_setup: SETUP(POSEDGE) load clko;
mem_d<0>_clko_setup: SETUP(POSEDGE) mem_d<0> clko;
mem_d<1>_clko_setup: SETUP(POSEDGE) mem_d<1> clko;
mem_d<2>_clko_setup: SETUP(POSEDGE) mem_d<2> clko;
mem_d<3>_clko_setup: SETUP(POSEDGE) mem_d<3> clko;
mem_d<4>_clko_setup: SETUP(POSEDGE) mem_d<4> clko;
mem_d<5>_clko_setup: SETUP(POSEDGE) mem_d<5> clko;
mem_d<6>_clko_setup: SETUP(POSEDGE) mem_d<6> clko;
mem_d<7>_clko_setup: SETUP(POSEDGE) mem_d<7> clko;
load_clko_hold: HOLD(POSEDGE) load clko;
mem_d<0>_clko_hold: HOLD(POSEDGE) mem_d<0> clko;
mem_d<1>_clko_hold: HOLD(POSEDGE) mem_d<1> clko;
mem_d<2>_clko_hold: HOLD(POSEDGE) mem_d<2> clko;
mem_d<3>_clko_hold: HOLD(POSEDGE) mem_d<3> clko;
mem_d<4>_clko_hold: HOLD(POSEDGE) mem_d<4> clko;
mem_d<5>_clko_hold: HOLD(POSEDGE) mem_d<5> clko;
mem_d<6>_clko_hold: HOLD(POSEDGE) mem_d<6> clko;
mem_d<7>_clko_hold: HOLD(POSEDGE) mem_d<7> clko;
datai_clki_setup: SETUP(POSEDGE) datai clki;
datai_clki_hold: HOLD(POSEDGE) datai clki;
eoc_clk_setup: SETUP(POSEDGE) eoc clk;
eoc_clk_hold: HOLD(POSEDGE) eoc clk;

ENDMODEL