ex24.rpt

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RPT
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    "address<12>".RSTF  =  rst
    "address<12>".PRLD  =  GND    

 "address<13>".T  =  "address<0>" * "address<11>" * "address<1>" * 
	"address<3>" * "address<5>" * "address<7>" * "address<12>" * 
	"address<2>" * "address<4>" * "address<6>" * 
	"address<8>.FBK".LFBK * "address<9>.FBK".LFBK * "address<10>.FBK".LFBK * 
	/mem_f.PIN
    "address<13>".CLKF  =  /"current_state<3>"
    "address<13>".RSTF  =  rst
    "address<13>".PRLD  =  GND    

 "address<14>".T  =  "address<0>" * "address<11>" * "address<1>" * 
	"address<3>" * "address<5>" * "address<7>" * "address<12>" * 
	"address<2>" * "address<4>" * "address<6>" * 
	"address<8>.FBK".LFBK * "address<9>.FBK".LFBK * "address<10>.FBK".LFBK * 
	"address<13>.FBK".LFBK * /mem_f.PIN
    "address<14>".CLKF  =  /"current_state<3>"
    "address<14>".RSTF  =  rst
    "address<14>".PRLD  =  GND    

 "address<1>".T  =  "address<0>.FBK".LFBK * /mem_f.PIN
    "address<1>".CLKF  =  /"current_state<3>.FBK".LFBK
    "address<1>".RSTF  =  rst
    "address<1>".PRLD  =  GND    

 "address<2>".T  =  "address<0>.FBK".LFBK * "address<1>.FBK".LFBK * 
	/mem_f.PIN
    "address<2>".CLKF  =  /"current_state<3>.FBK".LFBK
    "address<2>".RSTF  =  rst
    "address<2>".PRLD  =  GND    

 "address<3>".T  =  "address<0>.FBK".LFBK * "address<1>.FBK".LFBK * 
	"address<2>.FBK".LFBK * /mem_f.PIN
    "address<3>".CLKF  =  /"current_state<3>.FBK".LFBK
    "address<3>".RSTF  =  rst
    "address<3>".PRLD  =  GND    

 "address<4>".T  =  "address<0>.FBK".LFBK * "address<1>.FBK".LFBK * 
	"address<2>.FBK".LFBK * "address<3>.FBK".LFBK * /mem_f.PIN
    "address<4>".CLKF  =  /"current_state<3>.FBK".LFBK
    "address<4>".RSTF  =  rst
    "address<4>".PRLD  =  GND    

 "address<5>".T  =  "address<0>.FBK".LFBK * "address<1>.FBK".LFBK * 
	"address<2>.FBK".LFBK * "address<3>.FBK".LFBK * "address<4>.FBK".LFBK * 
	/mem_f.PIN
    "address<5>".CLKF  =  /"current_state<3>.FBK".LFBK
    "address<5>".RSTF  =  rst
    "address<5>".PRLD  =  GND    

 "address<6>".T  =  "address<0>.FBK".LFBK * "address<1>.FBK".LFBK * 
	"address<2>.FBK".LFBK * "address<3>.FBK".LFBK * "address<4>.FBK".LFBK * 
	"address<5>.FBK".LFBK * /mem_f.PIN
    "address<6>".CLKF  =  /"current_state<3>.FBK".LFBK
    "address<6>".RSTF  =  rst
    "address<6>".PRLD  =  GND    

 "address<7>".T  =  "address<0>.FBK".LFBK * "address<1>.FBK".LFBK * 
	"address<2>.FBK".LFBK * "address<3>.FBK".LFBK * "address<4>.FBK".LFBK * 
	"address<5>.FBK".LFBK * "address<6>.FBK".LFBK * /mem_f.PIN
    "address<7>".CLKF  =  /"current_state<3>.FBK".LFBK
    "address<7>".RSTF  =  rst
    "address<7>".PRLD  =  GND    

 "address<8>".T  =  "address<0>" * "address<1>" * "address<3>" * 
	"address<5>" * "address<7>" * "address<2>" * "address<4>" * 
	"address<6>" * /mem_f.PIN
    "address<8>".CLKF  =  /"current_state<3>"
    "address<8>".RSTF  =  rst
    "address<8>".PRLD  =  GND    

 "address<9>".T  =  "address<0>" * "address<1>" * "address<3>" * 
	"address<5>" * "address<7>" * "address<2>" * "address<4>" * 
	"address<6>" * "address<8>.FBK".LFBK * /mem_f.PIN
    "address<9>".CLKF  =  /"current_state<3>"
    "address<9>".RSTF  =  rst
    "address<9>".PRLD  =  GND    

 "current_state<0>"  :=  "current_state<0>.FBK".LFBK * mem_f.PIN
	+ "current_state<4>.FBK".LFBK * /mem_f.PIN
    "current_state<0>".CLKF  =  clk	;FCLK/GCK
    "current_state<0>".SETF  =  rst
    "current_state<0>".PRLD  =  GND    

 start  :=  "current_state<1>.FBK".LFBK * mem_f.PIN
	+ "current_state<0>.FBK".LFBK * /mem_f.PIN
    start.CLKF  =  clk	;FCLK/GCK
    start.RSTF  =  rst
    start.PRLD  =  GND    

 "current_state<2>".T  =  "current_state<1>.FBK".LFBK * 
	/"current_state<2>.FBK".LFBK * /mem_f.PIN
	+ eoc * /"current_state<1>.FBK".LFBK * 
	"current_state<2>.FBK".LFBK * /mem_f.PIN
    "current_state<2>".CLKF  =  clk	;FCLK/GCK
    "current_state<2>".RSTF  =  rst
    "current_state<2>".PRLD  =  GND    

 "current_state<3>"  :=  "current_state<3>.FBK".LFBK * mem_f.PIN
	+ eoc * "current_state<2>.FBK".LFBK * /mem_f.PIN
    "current_state<3>".CLKF  =  clk	;FCLK/GCK
    "current_state<3>".RSTF  =  rst
    "current_state<3>".PRLD  =  GND    

 "current_state<4>"  :=  "current_state<3>.FBK".LFBK * /mem_f.PIN
	+ "current_state<4>.FBK".LFBK * mem_f.PIN
    "current_state<4>".CLKF  =  clk	;FCLK/GCK
    "current_state<4>".RSTF  =  rst
    "current_state<4>".PRLD  =  GND    

 "saddress<0>"  :=  datai
    "saddress<0>".CLKF  =  clki
    "saddress<0>".PRLD  =  GND    

 "saddress<10>"  :=  "saddress<9>"
    "saddress<10>".CLKF  =  clki
    "saddress<10>".PRLD  =  GND    

 "saddress<11>"  :=  "saddress<10>.FBK".LFBK
    "saddress<11>".CLKF  =  clki
    "saddress<11>".PRLD  =  GND    

 "saddress<12>"  :=  "saddress<11>.FBK".LFBK
    "saddress<12>".CLKF  =  clki
    "saddress<12>".PRLD  =  GND    

 "saddress<13>"  :=  "saddress<12>.FBK".LFBK
    "saddress<13>".CLKF  =  clki
    "saddress<13>".PRLD  =  GND    

 "saddress<14>"  :=  "saddress<13>.FBK".LFBK
    "saddress<14>".CLKF  =  clki
    "saddress<14>".PRLD  =  GND    

 "saddress<1>"  :=  "saddress<0>.FBK".LFBK
    "saddress<1>".CLKF  =  clki
    "saddress<1>".PRLD  =  GND    

 "saddress<2>"  :=  "saddress<1>"
    "saddress<2>".CLKF  =  clki
    "saddress<2>".PRLD  =  GND    

 "saddress<3>"  :=  "saddress<2>.FBK".LFBK
    "saddress<3>".CLKF  =  clki
    "saddress<3>".PRLD  =  GND    

 "saddress<4>"  :=  "saddress<3>"
    "saddress<4>".CLKF  =  clki
    "saddress<4>".PRLD  =  GND    

 "saddress<5>"  :=  "saddress<4>.FBK".LFBK
    "saddress<5>".CLKF  =  clki
    "saddress<5>".PRLD  =  GND    

 "saddress<6>"  :=  "saddress<5>"
    "saddress<6>".CLKF  =  clki
    "saddress<6>".PRLD  =  GND    

 "saddress<7>"  :=  "saddress<6>.FBK".LFBK
    "saddress<7>".CLKF  =  clki
    "saddress<7>".PRLD  =  GND    

 "saddress<8>"  :=  "saddress<7>"
    "saddress<8>".CLKF  =  clki
    "saddress<8>".PRLD  =  GND    

 "saddress<9>"  :=  "saddress<8>.FBK".LFBK
    "saddress<9>".CLKF  =  clki
    "saddress<9>".PRLD  =  GND    

 "sbuf<0>"  :=  load * "mem_d<0>".PIN
	+ /load * "sbuf<0>.FBK".LFBK
    "sbuf<0>".CLKF  =  clko
    "sbuf<0>".PRLD  =  GND    

 "sbuf<1>"  :=  load * "mem_d<1>".PIN
	+ /load * "sbuf<0>.FBK".LFBK
    "sbuf<1>".CLKF  =  clko
    "sbuf<1>".PRLD  =  GND    

 "sbuf<2>"  :=  load * "mem_d<2>".PIN
	+ /load * "sbuf<1>.FBK".LFBK
    "sbuf<2>".CLKF  =  clko
    "sbuf<2>".PRLD  =  GND    

 "sbuf<3>"  :=  load * "mem_d<3>".PIN
	+ /load * "sbuf<2>.FBK".LFBK
    "sbuf<3>".CLKF  =  clko
    "sbuf<3>".PRLD  =  GND    

 "sbuf<4>"  :=  load * "mem_d<4>".PIN
	+ /load * "sbuf<3>.FBK".LFBK
    "sbuf<4>".CLKF  =  clko
    "sbuf<4>".PRLD  =  GND    

 "sbuf<5>"  :=  load * "mem_d<5>".PIN
	+ /load * "sbuf<4>.FBK".LFBK
    "sbuf<5>".CLKF  =  clko
    "sbuf<5>".PRLD  =  GND    

 "sbuf<6>"  :=  load * "mem_d<6>".PIN
	+ /load * "sbuf<5>.FBK".LFBK
    "sbuf<6>".CLKF  =  clko
    "sbuf<6>".PRLD  =  GND    

****************************  Device Pin Out ****************************

Device : XC9572-7-PC84


                                                              m  m     
                                                              e  e     
                                                     m  m     m  m     
                                m              d  d  e  e     _  _     
                                e  l     c  c  a  a  m  m     d  d     
        T  c  T  G  T  T  T  r  m  o  T  l  l  t  t  _  _  V  <  <  T  
        I  l  I  N  I  I  I  s  _  a  I  k  k  a  a  r  w  C  7  6  I  
        E  k  E  D  E  E  E  t  f  d  E  i  o  i  o  d  r  C  >  >  E  
        --------------------------------------------------------------  
       /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
  TIE | 12                                                          74 | TIE
  TIE | 13                                                          73 | VCC
  TIE | 14                                                          72 | mem_d<5>
   oe | 15                                                          71 | mem_d<3>
  GND | 16                                                          70 | mem_d<4>
  TIE | 17                                                          69 | mem_d<1>
  eoc | 18                                                          68 | mem_d<2>
start | 19                                                          67 | TIE
  TIE | 20                                                          66 | mem_d<0>
clock | 21                        XC9572-7-PC84                     65 | mem_a<14>
  VCC | 22                                                          64 | VCC
  TIE | 23                                                          63 | mem_a<12>
  TIE | 24                                                          62 | mem_a<13>
  TIE | 25                                                          61 | mem_a<11>
  TIE | 26                                                          60 | GND
  GND | 27                                                          59 | TDO
  TDI | 28                                                          58 | mem_a<10>
  TMS | 29                                                          57 | mem_a<7>
  TCK | 30                                                          56 | mem_a<8>
  TIE | 31                                                          55 | mem_a<6>
  TIE | 32                                                          54 | TIE
      \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
        --------------------------------------------------------------  
        d  T  d  d  d  V  d  d  d  G  d  T  m  m  m  m  G  T  m  m  m  
        i  I  i  i  i  C  i  i  i  N  i  I  e  e  e  e  N  I  e  e  e  
        n  E  n  n  n  C  n  n  n  D  n  E  m  m  m  m  D  E  m  m  m  
        <     <  <  <     <  <  <     <     _  _  _  _        _  _  _  
        1     2  0  3     5  4  6     7     a  a  a  a        a  a  a  
        >     >  >  >     >  >  >     >     <  <  <  <        <  <  <  
                                            0  1  2  3        4  9  5  
                                            >  >  >  >        >  >  >  


Legend :  NC  = Not Connected, unbonded pin
         TIE  = Tie pin to GND or board trace driven to valid logic level
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC9572-7-PC84
Use Timing Constraints                      : ON
Use Design Location Constraints             : ON
Create Programmable Ground Pins             : OFF
Use Advanced Fitting                        : ON
Use Local Feedback                          : ON
Use Pin Feedback                            : ON
Default Power Setting                       : STD
Default Output Slew Rate                    : FAST
Guide File Used                             : NONE
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : ON
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Global Clock(GCK) Optimization              : ON
Global Set/Reset(GSR) Optimization          : ON
Global Output Enable(GTS) Optimization      : ON
Collapsing pterm limit                      : 25
Collapsing input limit                      : 36
123

ex24.rpt - 源码说明

本页面展示了「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][」中的 ex24.rpt 源码文件，采用 RPT 编程语言编写，共 876 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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