time_sim.edn

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 1,661 行 · 第 1/5 页

            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_and7
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port IN3
              (direction INPUT)
            )
            (port IN4
              (direction INPUT)
            )
            (port IN5
              (direction INPUT)
            )
            (port IN6
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_bpad
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port PAD
              (direction INOUT)
            )
          )
      )
    )
    (cell x_tri
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port CTL
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_inv
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
  )

  (library ex24_lib
    (edifLevel 0)
    (technology (numberDefinition
      (scale 1 (E 1 -12) (unit TIME))))
    (cell ex24
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port clk
              (direction INPUT)
              (designator "10")
            )
            (port rst
              (direction INPUT)
              (designator "4")
            )
            (port (rename mem_a_1__ "mem_a<1>")
              (direction OUTPUT)
              (designator "46")
            )
            (port eoc
              (direction INPUT)
              (designator "18")
            )
            (port (rename mem_a_0__ "mem_a<0>")
              (direction OUTPUT)
              (designator "45")
            )
            (port mem_wr
              (direction OUTPUT)
              (designator "79")
            )
            (port (rename din_0__ "din<0>")
              (direction INPUT)
              (designator "36")
            )
            (port (rename din_1__ "din<1>")
              (direction INPUT)
              (designator "33")
            )
            (port (rename din_2__ "din<2>")
              (direction INPUT)
              (designator "35")
            )
            (port (rename din_3__ "din<3>")
              (direction INPUT)
              (designator "37")
            )
            (port (rename din_4__ "din<4>")
              (direction INPUT)
              (designator "40")
            )
            (port (rename din_5__ "din<5>")
              (direction INPUT)
              (designator "39")
            )
            (port (rename din_6__ "din<6>")
              (direction INPUT)
              (designator "41")
            )
            (port (rename din_7__ "din<7>")
              (direction INPUT)
              (designator "43")
            )
            (port datai
              (direction INPUT)
              (designator "82")
            )
            (port clki
              (direction INPUT)
              (designator "84")
            )
            (port load
              (direction INPUT)
              (designator "2")
            )
            (port clko
              (direction INPUT)
              (designator "83")
            )
            (port (rename mem_d_0__ "mem_d<0>")
              (direction INOUT)
              (designator "66")
            )
            (port mem_rd
              (direction OUTPUT)
              (designator "80")
            )
            (port (rename mem_d_1__ "mem_d<1>")
              (direction INOUT)
              (designator "69")
            )
            (port (rename mem_d_2__ "mem_d<2>")
              (direction INOUT)
              (designator "68")
            )
            (port clock
              (direction OUTPUT)
              (designator "21")
            )
            (port (rename mem_d_3__ "mem_d<3>")
              (direction INOUT)
              (designator "71")
            )
            (port start
              (direction OUTPUT)
              (designator "19")
            )
            (port (rename mem_d_4__ "mem_d<4>")
              (direction INOUT)
              (designator "70")
            )
            (port mem_f
              (direction OUTPUT)
              (designator "3")
            )
            (port (rename mem_d_5__ "mem_d<5>")
              (direction INOUT)
              (designator "72")
            )
            (port oe
              (direction OUTPUT)
              (designator "15")
            )
            (port (rename mem_d_6__ "mem_d<6>")
              (direction INOUT)
              (designator "76")
            )
            (port (rename mem_d_7__ "mem_d<7>")
              (direction INOUT)
              (designator "77")
            )
            (port datao
              (direction OUTPUT)
              (designator "81")
            )
            (port (rename mem_a_13__ "mem_a<13>")
              (direction OUTPUT)
              (designator "62")
            )
            (port (rename mem_a_12__ "mem_a<12>")
              (direction OUTPUT)
              (designator "63")
            )
            (port (rename mem_a_11__ "mem_a<11>")
              (direction OUTPUT)
              (designator "61")
            )
            (port (rename mem_a_10__ "mem_a<10>")
              (direction OUTPUT)
              (designator "58")
            )
            (port (rename mem_a_9__ "mem_a<9>")
              (direction OUTPUT)
              (designator "52")
            )
            (port (rename mem_a_8__ "mem_a<8>")
              (direction OUTPUT)
              (designator "56")
            )
            (port (rename mem_a_7__ "mem_a<7>")
              (direction OUTPUT)
              (designator "57")
            )
            (port (rename mem_a_6__ "mem_a<6>")
              (direction OUTPUT)
              (designator "55")
            )
            (port (rename mem_a_14__ "mem_a<14>")
              (direction OUTPUT)
              (designator "65")
            )
            (port (rename mem_a_5__ "mem_a<5>")
              (direction OUTPUT)
              (designator "53")
            )
            (port (rename mem_a_4__ "mem_a<4>")
              (direction OUTPUT)
              (designator "51")
            )
            (port (rename mem_a_3__ "mem_a<3>")
              (direction OUTPUT)
              (designator "48")
            )
            (port (rename mem_a_2__ "mem_a<2>")
              (direction OUTPUT)
              (designator "47")
            )
            (designator "XC9572-7-PC84")
          )
          (contents
            (instance start_PAD
              (viewRef view_1 (cellRef x_opad (libraryRef SIMPRIMS)))
            )
            (instance start_4
              (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS)))
              (portInstance OUT
                (property RISE (integer 2500) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 2500) (unit TIME) (owner "Xilinx"))
              )
            )
            (instance current_state_1__Q_5
              (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS)))
            )
            (instance current_state_1__R_OR_PRLD_6
              (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS)))
            )
            (instance current_state_1__REG
              (viewRef view_1 (cellRef x_ff (libraryRef SIMPRIMS)))
              (property SUINHICLK (integer 1500) (unit TIME) (owner "Xilinx"))
              (property SUINLOCLK (integer 1500) (unit TIME) (owner "Xilinx"))
              (property HOLDINHICLK (integer 3000) (unit TIME) (owner "Xilinx"))
              (property HOLDINLOCLK (integer 3000) (unit TIME) (owner "Xilinx"))
              (property PWCLKHI (integer 4000) (unit TIME) (owner "Xilinx"))
              (property PWCLKLO (integer 4000) (unit TIME) (owner "Xilinx"))
              (portInstance RST
                (property RISE (integer 6000) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 6000) (unit TIME) (owner "Xilinx"))
              )
              (portInstance OUT
                (property RISE (integer 500) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 500) (unit TIME) (owner "Xilinx"))
              )
            )
            (instance VCC_ONE
              (viewRef view_1 (cellRef x_one (libraryRef SIMPRIMS)))
            )
            (instance current_state_1__RSTF_PT_0_7
              (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS)))
              (portInstance IN0
                (property RISE (integer 2000) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 2000) (unit TIME) (owner "Xilinx"))
              )
              (portInstance IN1
                (property RISE (integer 2000) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 2000) (unit TIME) (owner "Xilinx"))
              )
            )
            (instance current_state_1__RSTF_8
              (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS)))
            )
            (instance GND_ZERO
              (viewRef view_1 (cellRef x_zero (libraryRef SIMPRIMS)))
            )
            (instance current_state_1__D1_9
              (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS)))
            )
            (instance current_state_1__D2_PT_0_10
              (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS)))