ex24.rpt
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 876 行 · 第 1/3 页
RPT
876 行
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 20/16
Number of signals used by logic mapping into function block: 20
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
saddress<7> 2 0 0 3 FB3_1 STD 25 I/O (b)
saddress<6> 2 0 0 3 FB3_2 STD 17 I/O (b)
N_din<7>$BUF0/N_din<7>$BUF0_TRST
2 0 0 3 FB3_3 STD 31 I/O (b)
current_state<4> 3 0 0 2 FB3_4 STD 32 I/O (b)
start 3 0 0 2 FB3_5 STD 19 I/O O
current_state<3> 3 0 0 2 FB3_6 STD 34 I/O (b)
current_state<2> 3 0 0 2 FB3_7 STD 35 I/O I
clock 1 0 0 4 FB3_8 STD 21 I/O O
current_state<0> 3 0 0 2 FB3_9 STD 26 I/O (b)
address<7> 3 0 0 2 FB3_10 STD 40 I/O I
address<6> 3 0 0 2 FB3_11 STD 33 I/O I
address<5> 3 0 0 2 FB3_12 STD 41 I/O I
address<4> 3 0 0 2 FB3_13 STD 43 I/O I
address<3> 3 0 0 2 FB3_14 STD 36 I/O I
address<2> 3 0 0 2 FB3_15 STD 37 I/O I
mem_a<0> 2 0 0 3 FB3_16 STD 45 I/O O
address<1> 3 0 0 2 FB3_17 STD 39 I/O I
address<0> 3 0 0 2 FB3_18 STD (b) (b)
Signals Used by Logic in Function Block
1: clk 8: "address<3>.FBK".LFBK
15: "current_state<3>.FBK".LFBK
2: clki 9: "address<4>.FBK".LFBK
16: "current_state<4>.FBK".LFBK
3: eoc 10: "address<5>.FBK".LFBK
17: mem_f.PIN
4: rst 11: "address<6>.FBK".LFBK
18: "saddress<0>"
5: "address<0>.FBK".LFBK
12: "current_state<0>.FBK".LFBK
19: "saddress<5>"
6: "address<1>.FBK".LFBK
13: "current_state<1>.FBK".LFBK
20: "saddress<6>.FBK".LFBK
7: "address<2>.FBK".LFBK
14: "current_state<2>.FBK".LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
saddress<7> .X.................X.................... 2 2
saddress<6> .X................X..................... 2 2
N_din<7>$BUF0/N_din<7>$BUF0_TRST
...X..........XX........................ 3 3
current_state<4> ...X..........XXX....................... 4 4
start ...X.......XX...X....................... 4 4
current_state<3> ..XX.........XX.X....................... 5 5
current_state<2> ..XX........XX..X....................... 5 5
clock X....................................... 1 1
current_state<0> ...X.......X...XX....................... 4 4
address<7> ...XXXXXXXX...X.X....................... 10 10
address<6> ...XXXXXXX....X.X....................... 9 9
address<5> ...XXXXXX.....X.X....................... 8 8
address<4> ...XXXXX......X.X....................... 7 7
address<3> ...XXXX.......X.X....................... 6 6
address<2> ...XXX........X.X....................... 5 5
mem_a<0> ...XX............X...................... 3 3
address<1> ...XX.........X.X....................... 4 4
address<0> ...X..........X.X....................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 33/3
Number of signals used by logic mapping into function block: 33
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
mem_a<1> 2 0 0 3 FB4_1 STD 46 I/O O
saddress<3> 2 0 0 3 FB4_2 STD 44 I/O (b)
mem_a<4> 2 0 0 3 FB4_3 STD 51 I/O O
mem_a<9> 2 0 0 3 FB4_4 STD 52 I/O O
mem_a<2> 2 0 0 3 FB4_5 STD 47 I/O O
saddress<2> 2 0 0 3 FB4_6 STD 54 I/O (b)
mem_a<6> 2 0 0 3 FB4_7 STD 55 I/O O
mem_a<3> 2 0 0 3 FB4_8 STD 48 I/O O
address<12> 3 0 0 2 FB4_9 STD 50 I/O (b)
mem_a<7> 2 0 0 3 FB4_10 STD 57 I/O O
mem_a<5> 2 0 0 3 FB4_11 STD 53 I/O O
mem_a<10> 2 0 0 3 FB4_12 STD 58 I/O O
mem_a<11> 2 0 0 3 FB4_13 STD 61 I/O O
mem_a<8> 2 0 0 3 FB4_14 STD 56 I/O O
mem_a<14> 2 0 0 3 FB4_15 STD 65 I/O O
mem_a<13> 2 0 0 3 FB4_16 STD 62 I/O O
mem_d<0> 2 0 0 3 FB4_17 STD 66 I/O I/O
address<11> 3 0 0 2 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: clki 12: "address<3>" 23: "saddress<13>"
2: "din<0>" 13: "address<4>" 24: "saddress<14>"
3: "N_din<7>$BUF0/N_din<7>$BUF0_TRST"
14: "address<5>" 25: "saddress<1>"
4: rst 15: "address<6>" 26: "saddress<2>.FBK".LFBK
5: "address<0>" 16: "address<7>" 27: "saddress<3>.FBK".LFBK
6: "address<10>" 17: "address<8>" 28: "saddress<4>"
7: "address<11>.FBK".LFBK
18: "address<9>" 29: "saddress<5>"
8: "address<13>" 19: "current_state<3>"
30: "saddress<6>"
9: "address<14>" 20: mem_f.PIN 31: "saddress<7>"
10: "address<1>" 21: "saddress<10>" 32: "saddress<8>"
11: "address<2>" 22: "saddress<11>" 33: "saddress<9>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
mem_a<1> ...X.....X..............X............... 3 3
saddress<3> X........................X.............. 2 2
mem_a<4> ...X........X..............X............ 3 3
mem_a<9> ...X.............X..............X....... 3 3
mem_a<2> ...X......X..............X.............. 3 3
saddress<2> X.......................X............... 2 2
mem_a<6> ...X..........X..............X.......... 3 3
mem_a<3> ...X.......X..............X............. 3 3
address<12> ...XXXX..XXXXXXXXXXX.................... 15 15
mem_a<7> ...X...........X..............X......... 3 3
mem_a<5> ...X.........X..............X........... 3 3
mem_a<10> ...X.X..............X................... 3 3
mem_a<11> ...X..X..............X.................. 3 3
mem_a<8> ...X............X..............X........ 3 3
mem_a<14> ...X....X..............X................ 3 3
mem_a<13> ...X...X..............X................. 3 3
mem_d<0> .XX..................................... 2 2
address<11> ...XXX...XXXXXXXXXXX.................... 14 14
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"mem_a<13>" = rst * "saddress<13>"
+ /rst * "address<13>"
"mem_a<12>" = rst * "saddress<12>"
+ /rst * "address<12>"
"mem_a<11>" = rst * "saddress<11>"
+ /rst * "address<11>.FBK".LFBK
"mem_a<10>" = rst * "saddress<10>"
+ /rst * "address<10>"
"mem_a<9>" = rst * "saddress<9>"
+ /rst * "address<9>"
"mem_a<8>" = rst * "saddress<8>"
+ /rst * "address<8>"
"mem_a<7>" = rst * "saddress<7>"
+ /rst * "address<7>"
"mem_a<6>" = rst * "saddress<6>"
+ /rst * "address<6>"
"mem_a<14>" = rst * "saddress<14>"
+ /rst * "address<14>"
"mem_a<5>" = rst * "saddress<5>"
+ /rst * "address<5>"
"mem_a<4>" = rst * "saddress<4>"
+ /rst * "address<4>"
"mem_a<3>" = rst * "saddress<3>.FBK".LFBK
+ /rst * "address<3>"
"mem_a<2>" = rst * "saddress<2>.FBK".LFBK
+ /rst * "address<2>"
"mem_a<1>" = rst * "saddress<1>"
+ /rst * "address<1>"
"mem_a<0>" = rst * "saddress<0>"
+ /rst * "address<0>.FBK".LFBK
/mem_wr = /rst * "current_state<3>"
mem_rd = /rst
/oe = /"current_state<3>" * /"current_state<4>"
clock = clk
datao := load * "mem_d<7>".PIN
+ /load * "sbuf<6>"
datao.CLKF = clko
datao.PRLD = GND
"mem_d<0>" = "din<0>"
"mem_d<0>".TRST = "N_din<7>$BUF0/N_din<7>$BUF0_TRST"
"mem_d<1>" = "din<1>"
"mem_d<1>".TRST = "N_din<7>$BUF0/N_din<7>$BUF0_TRST"
"mem_d<2>" = "din<2>"
"mem_d<2>".TRST = "N_din<7>$BUF0/N_din<7>$BUF0_TRST"
"mem_d<3>" = "din<3>"
"mem_d<3>".TRST = "N_din<7>$BUF0/N_din<7>$BUF0_TRST"
"mem_d<4>" = "din<4>"
"mem_d<4>".TRST = "N_din<7>$BUF0/N_din<7>$BUF0_TRST"
"mem_d<5>" = "din<5>"
"mem_d<5>".TRST = "N_din<7>$BUF0/N_din<7>$BUF0_TRST"
"mem_d<6>" = "din<6>"
"mem_d<6>".TRST = "N_din<7>$BUF0/N_din<7>$BUF0_TRST"
"mem_d<7>" = "din<7>"
"mem_d<7>".TRST = "N_din<7>$BUF0/N_din<7>$BUF0_TRST"
"N_din<7>$BUF0/N_din<7>$BUF0_TRST" = /rst * "current_state<3>.FBK".LFBK
+ /rst * "current_state<4>.FBK".LFBK
mem_f := Vcc
mem_f.CLKF = /"address<14>"
mem_f.RSTF = rst
mem_f.PRLD = GND
/"address<0>".T = mem_f.PIN
"address<0>".CLKF = /"current_state<3>.FBK".LFBK
"address<0>".RSTF = rst
"address<0>".PRLD = GND
"address<10>".T = "address<0>" * "address<1>" * "address<3>" *
"address<5>" * "address<7>" * "address<2>" * "address<4>" *
"address<6>" * "address<8>.FBK".LFBK * "address<9>.FBK".LFBK *
/mem_f.PIN
"address<10>".CLKF = /"current_state<3>"
"address<10>".RSTF = rst
"address<10>".PRLD = GND
"address<11>".T = "address<0>" * "address<1>" * "address<3>" *
"address<5>" * "address<7>" * "address<9>" * "address<10>" *
"address<2>" * "address<4>" * "address<6>" * "address<8>" *
/mem_f.PIN
"address<11>".CLKF = /"current_state<3>"
"address<11>".RSTF = rst
"address<11>".PRLD = GND
"address<12>".T = "address<0>" * "address<1>" * "address<3>" *
"address<5>" * "address<7>" * "address<9>" * "address<10>" *
"address<2>" * "address<4>" * "address<6>" * "address<8>" *
"address<11>.FBK".LFBK * /mem_f.PIN
"address<12>".CLKF = /"current_state<3>"
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