ex24.rpt
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RPT
876 行
cpldfit: version E.38 Xilinx Inc.
Fitter Report
Design Name: ex24 Date: 3-12-2008, 9:13AM
Device Used: XC9572-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
72 /72 (100%) 168 /360 ( 46%) 44 /72 ( 61%) 45 /69 ( 65%) 115/144 ( 79%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 14 14 | I/O : 42 21
Output : 21 21 | GCK/IO : 1 2
Bidirectional : 9 9 | GTS/IO : 2 0
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 45 45
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 44
Non-registered Macrocell driving I/O 27
GLOBAL RESOURCES:
Signal 'clk' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 72 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 72 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
N_din<7>$BUF0/N_din<7>$BUF0_TRST 2 3 FB3_3 STD 31 I/O (b)
address<0> 3 3 FB3_18 STD (b) (b)
address<10> 3 13 FB2_18 STD (b) (b)
address<11> 3 14 FB4_18 STD (b) (b)
address<12> 3 15 FB4_9 STD 50 I/O (b)
address<13> 3 16 FB2_17 STD 84 I/O I
address<14> 3 17 FB2_16 STD 82 I/O I
address<1> 3 4 FB3_17 STD 39 I/O I
address<2> 3 5 FB3_15 STD 37 I/O I
address<3> 3 6 FB3_14 STD 36 I/O I
address<4> 3 7 FB3_13 STD 43 I/O I
address<5> 3 8 FB3_12 STD 41 I/O I
address<6> 3 9 FB3_11 STD 33 I/O I
address<7> 3 10 FB3_10 STD 40 I/O I
address<8> 3 11 FB2_15 STD 83 I/O I
address<9> 3 12 FB2_10 STD 75 I/O (b)
clock 1 1 FB3_8 STD FAST 21 I/O O
current_state<0> 3 4 FB3_9 STD 26 I/O (b)
current_state<2> 3 5 FB3_7 STD 35 I/O I
current_state<3> 3 5 FB3_6 STD 34 I/O (b)
current_state<4> 3 4 FB3_4 STD 32 I/O (b)
datao 3 4 FB2_14 STD FAST 81 I/O O
mem_a<0> 2 3 FB3_16 STD FAST 45 I/O O
mem_a<10> 2 3 FB4_12 STD FAST 58 I/O O
mem_a<11> 2 3 FB4_13 STD FAST 61 I/O O
mem_a<12> 2 3 FB2_1 STD FAST 63 I/O O
mem_a<13> 2 3 FB4_16 STD FAST 62 I/O O
mem_a<14> 2 3 FB4_15 STD FAST 65 I/O O
mem_a<1> 2 3 FB4_1 STD FAST 46 I/O O
mem_a<2> 2 3 FB4_5 STD FAST 47 I/O O
mem_a<3> 2 3 FB4_8 STD FAST 48 I/O O
mem_a<4> 2 3 FB4_3 STD FAST 51 I/O O
mem_a<5> 2 3 FB4_11 STD FAST 53 I/O O
mem_a<6> 2 3 FB4_7 STD FAST 55 I/O O
mem_a<7> 2 3 FB4_10 STD FAST 57 I/O O
mem_a<8> 2 3 FB4_14 STD FAST 56 I/O O
mem_a<9> 2 3 FB4_4 STD FAST 52 I/O O
mem_d<0> 2 2 FB4_17 STD FAST 66 I/O I/O
mem_d<1> 2 2 FB2_2 STD FAST 69 I/O I/O
mem_d<2> 2 2 FB2_4 STD FAST 68 I/O I/O
mem_d<3> 2 2 FB2_6 STD FAST 71 I/O I/O
mem_d<4> 2 2 FB2_5 STD FAST 70 I/O I/O
mem_d<5> 2 2 FB2_8 STD FAST 72 I/O I/O
mem_d<6> 2 2 FB2_7 STD FAST 76 GTS/I/O I/O
mem_d<7> 2 2 FB2_11 STD FAST 77 GTS/I/O I/O
mem_f 2 2 FB1_6 STD FAST 3 I/O I/O
mem_rd 1 1 FB2_13 STD FAST 80 I/O O
mem_wr 1 2 FB2_12 STD FAST 79 I/O O
oe 1 2 FB1_17 STD FAST 15 I/O O
saddress<0> 2 2 FB1_10 STD 13 I/O (b)
saddress<10> 2 2 FB1_9 STD 9 GCK/I/O (b)
saddress<11> 2 2 FB1_8 STD 5 I/O (b)
saddress<12> 2 2 FB1_7 STD 11 I/O (b)
saddress<13> 2 2 FB1_5 STD 2 I/O I
saddress<14> 2 2 FB1_4 STD 7 I/O (b)
saddress<1> 2 2 FB1_3 STD 6 I/O (b)
saddress<2> 2 2 FB4_6 STD 54 I/O (b)
saddress<3> 2 2 FB4_2 STD 44 I/O (b)
saddress<4> 2 2 FB1_2 STD 1 I/O (b)
saddress<5> 2 2 FB1_1 STD 4 I/O I
saddress<6> 2 2 FB3_2 STD 17 I/O (b)
saddress<7> 2 2 FB3_1 STD 25 I/O (b)
saddress<8> 2 2 FB2_9 STD 74 GSR/I/O (b)
saddress<9> 2 2 FB2_3 STD 67 I/O (b)
sbuf<0> 3 4 FB1_18 STD 24 I/O (b)
sbuf<1> 3 4 FB1_16 STD 23 I/O (b)
sbuf<2> 3 4 FB1_15 STD 14 I/O (b)
sbuf<3> 3 4 FB1_14 STD 12 GCK/I/O (b)
sbuf<4> 3 4 FB1_13 STD 20 I/O (b)
sbuf<5> 3 4 FB1_12 STD 18 I/O I
sbuf<6> 3 4 FB1_11 STD 10 GCK/I/O GCK/I
start 3 4 FB3_5 STD FAST 19 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk FB1_11 10 GCK/I/O GCK/I
clki FB2_17 84 I/O I
clko FB2_15 83 I/O I
datai FB2_16 82 I/O I
din<0> FB3_14 36 I/O I
din<1> FB3_11 33 I/O I
din<2> FB3_7 35 I/O I
din<3> FB3_15 37 I/O I
din<4> FB3_10 40 I/O I
din<5> FB3_17 39 I/O I
din<6> FB3_12 41 I/O I
din<7> FB3_13 43 I/O I
eoc FB1_12 18 I/O I
load FB1_5 2 I/O I
rst FB1_1 4 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 18 29 29 42 1/1 18
FB2 18 33 33 40 4/7 17
FB3 18 20 20 48 3/0 17
FB4 18 33 33 38 13/1 17
---- ----- ----- -----
72 168 21/9 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 29/7
Number of signals used by logic mapping into function block: 29
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
saddress<5> 2 0 0 3 FB1_1 STD 4 I/O I
saddress<4> 2 0 0 3 FB1_2 STD 1 I/O (b)
saddress<1> 2 0 0 3 FB1_3 STD 6 I/O (b)
saddress<14> 2 0 0 3 FB1_4 STD 7 I/O (b)
saddress<13> 2 0 0 3 FB1_5 STD 2 I/O I
mem_f 2 0 0 3 FB1_6 STD 3 I/O I/O
saddress<12> 2 0 0 3 FB1_7 STD 11 I/O (b)
saddress<11> 2 0 0 3 FB1_8 STD 5 I/O (b)
saddress<10> 2 0 0 3 FB1_9 STD 9 GCK/I/O (b)
saddress<0> 2 0 0 3 FB1_10 STD 13 I/O (b)
sbuf<6> 3 0 0 2 FB1_11 STD 10 GCK/I/O GCK/I
sbuf<5> 3 0 0 2 FB1_12 STD 18 I/O I
sbuf<4> 3 0 0 2 FB1_13 STD 20 I/O (b)
sbuf<3> 3 0 0 2 FB1_14 STD 12 GCK/I/O (b)
sbuf<2> 3 0 0 2 FB1_15 STD 14 I/O (b)
sbuf<1> 3 0 0 2 FB1_16 STD 23 I/O (b)
oe 1 0 0 4 FB1_17 STD 15 I/O O
sbuf<0> 3 0 0 2 FB1_18 STD 24 I/O (b)
Signals Used by Logic in Function Block
1: clki 11: "mem_d<6>".PIN 21: "saddress<3>"
2: clko 12: rst 22: "saddress<4>.FBK".LFBK
3: datai 13: "address<14>" 23: "saddress<9>"
4: load 14: "current_state<3>"
24: "sbuf<0>.FBK".LFBK
5: "mem_d<0>".PIN 15: "current_state<4>"
25: "sbuf<1>.FBK".LFBK
6: "mem_d<1>".PIN 16: "saddress<0>.FBK".LFBK
26: "sbuf<2>.FBK".LFBK
7: "mem_d<2>".PIN 17: "saddress<10>.FBK".LFBK
27: "sbuf<3>.FBK".LFBK
8: "mem_d<3>".PIN 18: "saddress<11>.FBK".LFBK
28: "sbuf<4>.FBK".LFBK
9: "mem_d<4>".PIN 19: "saddress<12>.FBK".LFBK
29: "sbuf<5>.FBK".LFBK
10: "mem_d<5>".PIN 20: "saddress<13>.FBK".LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
saddress<5> X....................X.................. 2 2
saddress<4> X...................X................... 2 2
saddress<1> X..............X........................ 2 2
saddress<14> X..................X.................... 2 2
saddress<13> X.................X..................... 2 2
mem_f ...........XX........................... 2 2
saddress<12> X................X...................... 2 2
saddress<11> X...............X....................... 2 2
saddress<10> X.....................X................. 2 2
saddress<0> X.X..................................... 2 2
sbuf<6> .X.X......X.................X........... 4 4
sbuf<5> .X.X.....X.................X............ 4 4
sbuf<4> .X.X....X.................X............. 4 4
sbuf<3> .X.X...X.................X.............. 4 4
sbuf<2> .X.X..X.................X............... 4 4
sbuf<1> .X.X.X.................X................ 4 4
oe .............XX......................... 2 2
sbuf<0> .X.XX..................X................ 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 33/3
Number of signals used by logic mapping into function block: 33
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
mem_a<12> 2 0 0 3 FB2_1 STD 63 I/O O
mem_d<1> 2 0 0 3 FB2_2 STD 69 I/O I/O
saddress<9> 2 0 0 3 FB2_3 STD 67 I/O (b)
mem_d<2> 2 0 0 3 FB2_4 STD 68 I/O I/O
mem_d<4> 2 0 0 3 FB2_5 STD 70 I/O I/O
mem_d<3> 2 0 0 3 FB2_6 STD 71 I/O I/O
mem_d<6> 2 0 0 3 FB2_7 STD 76 GTS/I/O I/O
mem_d<5> 2 0 0 3 FB2_8 STD 72 I/O I/O
saddress<8> 2 0 0 3 FB2_9 STD 74 GSR/I/O (b)
address<9> 3 0 0 2 FB2_10 STD 75 I/O (b)
mem_d<7> 2 0 0 3 FB2_11 STD 77 GTS/I/O I/O
mem_wr 1 0 0 4 FB2_12 STD 79 I/O O
mem_rd 1 0 0 4 FB2_13 STD 80 I/O O
datao 3 0 0 2 FB2_14 STD 81 I/O O
address<8> 3 0 0 2 FB2_15 STD 83 I/O I
address<14> 3 0 0 2 FB2_16 STD 82 I/O I
address<13> 3 0 0 2 FB2_17 STD 84 I/O I
address<10> 3 0 0 2 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: clki 12: "mem_d<7>".PIN 23: "address<5>"
2: clko 13: rst 24: "address<6>"
3: "din<1>" 14: "address<0>" 25: "address<7>"
4: "din<2>" 15: "address<10>.FBK".LFBK
26: "address<8>.FBK".LFBK
5: "din<3>" 16: "address<11>" 27: "address<9>.FBK".LFBK
6: "din<4>" 17: "address<12>" 28: "current_state<3>"
7: "din<5>" 18: "address<13>.FBK".LFBK
29: mem_f.PIN
8: "din<6>" 19: "address<1>" 30: "saddress<12>"
9: "din<7>" 20: "address<2>" 31: "saddress<7>"
10: "N_din<7>$BUF0/N_din<7>$BUF0_TRST"
21: "address<3>" 32: "saddress<8>.FBK".LFBK
11: load 22: "address<4>" 33: "sbuf<6>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
mem_a<12> ............X...X............X.......... 3 3
mem_d<1> ..X......X.............................. 2 2
saddress<9> X..............................X........ 2 2
mem_d<2> ...X.....X.............................. 2 2
mem_d<4> .....X...X.............................. 2 2
mem_d<3> ....X....X.............................. 2 2
mem_d<6> .......X.X.............................. 2 2
mem_d<5> ......X..X.............................. 2 2
saddress<8> X.............................X......... 2 2
address<9> ............XX....XXXXXXXX.XX........... 12 12
mem_d<7> ........XX.............................. 2 2
mem_wr ............X..............X............ 2 2
mem_rd ............X........................... 1 1
datao .X........XX....................X....... 4 4
address<8> ............XX....XXXXXXX..XX........... 11 11
address<14> ............XXXXXXXXXXXXXXXXX........... 17 17
address<13> ............XXXXX.XXXXXXXXXXX........... 16 16
address<10> ............XX....XXXXXXXXXXX........... 13 13
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