ex24.tim
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· TIM 代码 · 共 407 行 · 第 1/2 页
TIM
407 行
datao.D 12.0
sbuf<0>.D 8.0
sbuf<1>.D 8.0
sbuf<2>.D 12.0
sbuf<3>.D 8.0
sbuf<4>.D 8.0
sbuf<5>.D 8.0
sbuf<6>.D 8.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: clki)
\ From s s s s s s s s s s s
\ a a a a a a a a a a a
\ d d d d d d d d d d d
\ d d d d d d d d d d d
\ r r r r r r r r r r r
\ e e e e e e e e e e e
\ s s s s s s s s s s s
\ s s s s s s s s s s s
\ < < < < < < < < < < <
\ 0 1 1 1 1 1 2 3 4 5 6
\ > 0 1 2 3 > > > > > >
\ . > > > > . . . . . .
\ Q . . . . Q Q Q Q Q Q
\ Q Q Q Q
To \------------------------------------------------------------------
saddress<10>.D
saddress<11>.D 8.0
saddress<12>.D 8.0
saddress<13>.D 8.0
saddress<14>.D 8.0
saddress<1>.D 8.0
saddress<2>.D 8.0
saddress<3>.D 12.0
saddress<4>.D 8.0
saddress<5>.D 8.0
saddress<6>.D 8.0
saddress<7>.D 8.0
saddress<8>.D
saddress<9>.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: clki)
\ From s s s
\ a a a
\ d d d
\ d d d
\ r r r
\ e e e
\ s s s
\ s s s
\ < < <
\ 7 8 9
\ > > >
\ . . .
\ Q Q Q
\
To \------------------
saddress<10>.D 12.0
saddress<11>.D
saddress<12>.D
saddress<13>.D
saddress<14>.D
saddress<1>.D
saddress<2>.D
saddress<3>.D
saddress<4>.D
saddress<5>.D
saddress<6>.D
saddress<7>.D
saddress<8>.D 8.0
saddress<9>.D 8.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: current_state<3>.Q)
\ From a a a a a a a a a a a
\ d d d d d d d d d d d
\ d d d d d d d d d d d
\ r r r r r r r r r r r
\ e e e e e e e e e e e
\ s s s s s s s s s s s
\ s s s s s s s s s s s
\ < < < < < < < < < < <
\ 0 1 1 1 1 1 2 3 4 5 6
\ > 0 1 2 3 > > > > > >
\ . > > > > . . . . . .
\ Q . . . . Q Q Q Q Q Q
\ Q Q Q Q
To \------------------------------------------------------------------
address<10>.D 12.0 12.0 12.0 12.0 12.0 12.0 12.0
address<11>.D 12.0 8.0 12.0 12.0 12.0 12.0 12.0 12.0
address<12>.D 12.0 8.0 8.0 12.0 12.0 12.0 12.0 12.0 12.0
address<13>.D 12.0 8.0 8.0 8.0 12.0 12.0 12.0 12.0 12.0 12.0
address<14>.D 12.0 8.0 8.0 8.0 8.0 12.0 12.0 12.0 12.0 12.0 12.0
address<1>.D 8.0
address<2>.D 12.0 12.0
address<3>.D 12.0 12.0 8.0
address<4>.D 12.0 12.0 8.0 8.0
address<5>.D 12.0 12.0 8.0 8.0 8.0
address<6>.D 12.0 12.0 8.0 8.0 8.0 8.0
address<7>.D 12.0 12.0 8.0 8.0 8.0 8.0 8.0
address<8>.D 12.0 12.0 12.0 12.0 12.0 12.0 12.0
address<9>.D 12.0 12.0 12.0 12.0 12.0 12.0 12.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: current_state<3>.Q)
\ From a a a
\ d d d
\ d d d
\ r r r
\ e e e
\ s s s
\ s s s
\ < < <
\ 7 8 9
\ > > >
\ . . .
\ Q Q Q
\
To \------------------
address<10>.D 12.0 8.0 8.0
address<11>.D 12.0 8.0 8.0
address<12>.D 12.0 8.0 8.0
address<13>.D 12.0 8.0 8.0
address<14>.D 12.0 8.0 8.0
address<1>.D
address<2>.D
address<3>.D
address<4>.D
address<5>.D
address<6>.D
address<7>.D
address<8>.D 12.0
address<9>.D 12.0 8.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: clk)
\ From c c c c s
\ u u u u t
\ r r r r a
\ r r r r r
\ e e e e t
\ n n n n .
\ t t t t Q
\ _ _ _ _
\ s s s s
\ t t t t
\ a a a a
\ t t t t
\ e e e e
\ < < < <
\ 0 2 3 4
\ > > > >
\ . . . .
\ Q Q Q Q
To \------------------------------
current_state<0>.D 8.0 8.0
current_state<2>.D 8.0 9.0
current_state<3>.D 8.0 8.0
current_state<4>.D 8.0 8.0
start.D 12.0 8.0
Path Type Definition:
Pad to Pad (tPD) - Reports pad to pad paths that start
at input pads and end at output pads.
Paths are not traced through
registers.
Clock Pad to Output Pad (tCO) - Reports paths that start at input
pads trace through clock inputs of
registers and end at output pads.
Paths are not traced through PRE/CLR
inputs of registers.
Setup to Clock at Pad (tSU) - Reports external setup time of data
to clock at pad. Data path starts at
an input pad and end at register D/T
input. Clock path starts at input pad
and ends at the register clock input.
Paths are not traced through
registers.
Clock to Setup (tCYC) - Register to register cycle time.
Include source register tCO and
destination register tSU.
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