ex24.tim

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                           Performance Summary Report
                           --------------------------

Design:     ex24
Device:     XC95108-7-PC84
Speed File: Version 3.0
Program:    Timing Report Generator:  version E.38
Date:       Wed Mar 12 09:15:37 2008

Performance Summary: 

Pad to Pad (tPD)                          :         20.0ns (2 macrocell levels)
Pad 'rst' to Pad 'mem_d<0>'                                       

Clock net 'clko' path delays:

Clock Pad to Output Pad (tCO)             :          8.5ns (1 macrocell levels)
Clock Pad 'clko' to Output Pad 'datao'                            (Pterm Clock)

Clock to Setup (tCYC)                     :         12.0ns (1 macrocell levels)
Clock to Q, net 'sbuf<1>.Q' to DFF Setup(D) at 'sbuf<2>.D'        (Pterm Clock)

Setup to Clock at the Pad (tSU)           :          0.5ns (0 macrocell levels)
Data signal 'load' to DFF D input Pin at 'sbuf<0>.D'
Clock pad 'clko'                                                  (Pterm Clock)

                          Minimum Clock Period: 12.0ns
                     Maximum Internal Clock Speed: 83.3Mhz
                            (Limited by Cycle Time)

Clock net 'clki' path delays:

Clock Pad to Output Pad (tCO)             :         19.0ns (2 macrocell levels)
Clock Pad 'clki' to Output Pad 'mem_a<13>'                        (Pterm Clock)

Clock to Setup (tCYC)                     :         12.0ns (1 macrocell levels)
Clock to Q, net 'saddress<9>.Q' to DFF Setup(D) at 'saddress<10>.D'(Pterm Clock)
Target FF drives output net 'saddress<10>'

Setup to Clock at the Pad (tSU)           :          0.5ns (0 macrocell levels)
Data signal 'datai' to DFF D input Pin at 'saddress<0>.D'
Clock pad 'clki'                                                  (Pterm Clock)

                          Minimum Clock Period: 12.0ns
                     Maximum Internal Clock Speed: 83.3Mhz
                            (Limited by Cycle Time)

Clock net 'address<14>.Q' path delays:

                          Minimum Clock Period: 10.0ns
                     Maximum Internal Clock Speed: 100.0Mhz
                         (Limited by Clock Pulse Width)

Clock net 'current_state<3>.Q' path delays:

Clock to Setup (tCYC)                     :         12.0ns (1 macrocell levels)
Clock to Q, net 'address<0>.Q' to TFF Setup(D) at 'address<11>.D' (Pterm Clock)
Target FF drives output net 'address<11>'

                          Minimum Clock Period: 12.0ns
                     Maximum Internal Clock Speed: 83.3Mhz
                            (Limited by Cycle Time)

Clock net 'clk' path delays:

Clock Pad to Output Pad (tCO)             :         27.5ns (1 macrocell levels)
Clock Pad 'clk' to Output Pad 'mem_f'                                     (GCK)

Clock to Setup (tCYC)                     :         12.0ns (1 macrocell levels)
Clock to Q, net 'current_state<0>.Q' to DFF Setup(D) at 'start.D'         (GCK)
Target FF drives output net 'current_state<1>$Q'

Setup to Clock at the Pad (tSU)           :          4.5ns (0 macrocell levels)
Data signal 'eoc' to DFF D input Pin at 'current_state<3>.D'
Clock pad 'clk'                                                           (GCK)

                          Minimum Clock Period: 12.0ns
                     Maximum Internal Clock Speed: 83.3Mhz
                            (Limited by Cycle Time)

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From        c     d     d     d     d     d     d     d     d     r
 \            l     i     i     i     i     i     i     i     i     s
  \           k     n     n     n     n     n     n     n     n     t
   \                <     <     <     <     <     <     <     <      
    \               0     1     2     3     4     5     6     7      
     \              >     >     >     >     >     >     >     >      
      \                                                              
       \                                                             
        \                                                            
  To     \------------------------------------------------------------

clock       7.5                                                      
mem_a<0>                                                          7.5
mem_a<10>                                                         7.5
mem_a<11>                                                         7.5
mem_a<12>                                                         7.5
mem_a<13>                                                         7.5
mem_a<14>                                                         7.5
mem_a<1>                                                          7.5
mem_a<2>                                                          7.5
mem_a<3>                                                          7.5
mem_a<4>                                                          7.5
mem_a<5>                                                          7.5
mem_a<6>                                                          7.5
mem_a<7>                                                          7.5
mem_a<8>                                                          7.5
mem_a<9>                                                          7.5
mem_d<0>          7.5                                            20.0
mem_d<1>                7.5                                      20.0
mem_d<2>                      7.5                                20.0
mem_d<3>                            7.5                          16.0
mem_d<4>                                  7.5                    20.0
mem_d<5>                                        7.5              16.0
mem_d<6>                                              7.5        16.0
mem_d<7>                                                    7.5  16.0
mem_rd                                                            7.5
mem_wr                                                            7.5

--------------------------------------------------------------------------------
                      Clock Pad to Output Pad (tCO) (nsec)

\ From        c     c     c
 \            l     l     l
  \           k     k     k
   \                i     o
    \                      
     \                     
      \                    
       \                   
        \                  
  To     \------------------

datao                   8.5
mem_a<0>   22.5  19.0      
mem_a<10>  26.5  19.0      
mem_a<11>  26.5  19.0      
mem_a<12>  26.5  19.0      
mem_a<13>  26.5  19.0      
mem_a<14>  26.5  19.0      
mem_a<1>   22.5  19.0      
mem_a<2>   26.5  19.0      
mem_a<3>   26.5  19.0      
mem_a<4>   26.5  19.0      
mem_a<5>   26.5  19.0      
mem_a<6>   26.5  19.0      
mem_a<7>   22.5  19.0      
mem_a<8>   22.5  19.0      
mem_a<9>   22.5  19.0      
mem_d<0>   23.5            
mem_d<1>   23.5            
mem_d<2>   23.5            
mem_d<3>   19.5            
mem_d<4>   23.5            
mem_d<5>   19.5            
mem_d<6>   19.5            
mem_d<7>   19.5            
mem_f      27.5            
mem_wr     11.0            
oe         15.0            
start       4.5            

--------------------------------------------------------------------------------
                       Setup to Clock at Pad (tSU) (nsec)

\ From       c     c     c
 \           l     l     l
  \          k     k     k
   \               i     o
    \                     
     \                    
      \                   
       \                  
  To    \------------------

datai            0.5      
eoc        4.5            
load                   0.5
mem_d<0>               0.5
mem_d<1>               0.5
mem_d<2>               0.5
mem_d<3>               0.5
mem_d<4>               0.5
mem_d<5>               0.5
mem_d<6>               0.5
mem_d<7>               0.5

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                 (Clock: clko)

\ From        s     s     s     s     s     s     s
 \            b     b     b     b     b     b     b
  \           u     u     u     u     u     u     u
   \          f     f     f     f     f     f     f
    \         <     <     <     <     <     <     <
     \        0     1     2     3     4     5     6
      \       >     >     >     >     >     >     >
       \      .     .     .     .     .     .     .
        \     Q     Q     Q     Q     Q     Q     Q
  To     \------------------------------------------