ex24.rpt

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 961 行 · 第 1/4 页

mem_a<1>              2       0     0   3     FB6_3   STD   46    I/O     O
(unused)              0       0     0   5     FB6_4               (b)     
mem_a<2>              2       0     0   3     FB6_5   STD   47    I/O     O
mem_a<3>              2       0     0   3     FB6_6   STD   48    I/O     O
address<9>            3       0     0   2     FB6_7   STD         (b)     (b)
address<8>            3       0     0   2     FB6_8   STD   50    I/O     (b)
mem_a<4>              2       0     0   3     FB6_9   STD   51    I/O     O
address<14>           3       0     0   2     FB6_10  STD         (b)     (b)
mem_a<9>              2       0     0   3     FB6_11  STD   52    I/O     O
mem_a<5>              2       0     0   3     FB6_12  STD   53    I/O     O
address<13>           3       0     0   2     FB6_13  STD         (b)     (b)
address<12>           3       0     0   2     FB6_14  STD   54    I/O     (b)
mem_a<6>              2       0     0   3     FB6_15  STD   55    I/O     O
address<11>           3       0     0   2     FB6_16  STD         (b)     (b)
mem_a<8>              2       0     0   3     FB6_17  STD   56    I/O     O
address<10>           3       0     0   2     FB6_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: rst               10: "address<4>"      19: "saddress<1>" 
  2: "address<0>"      11: "address<5>"      20: "saddress<2>" 
  3: "address<10>.FBK".LFBK 
                       12: "address<6>"      21: "saddress<3>" 
  4: "address<11>.FBK".LFBK 
                       13: "address<7>"      22: "saddress<4>" 
  5: "address<12>.FBK".LFBK 
                       14: "address<8>.FBK".LFBK 
                                             23: "saddress<5>" 
  6: "address<13>.FBK".LFBK 
                       15: "address<9>.FBK".LFBK 
                                             24: "saddress<6>" 
  7: "address<1>"      16: "current_state<3>" 
                                             25: "saddress<8>" 
  8: "address<2>"      17: mem_f.PIN         26: "saddress<9>" 
  9: "address<3>"      18: "saddress<0>"    

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
mem_a<0>             XX...............X...................... 3       3
mem_a<1>             X.....X...........X..................... 3       3
mem_a<2>             X......X...........X.................... 3       3
mem_a<3>             X.......X...........X................... 3       3
address<9>           XX....XXXXXXXX.XX....................... 12      12
address<8>           XX....XXXXXXX..XX....................... 11      11
mem_a<4>             X........X...........X.................. 3       3
address<14>          XXXXXXXXXXXXXXXXX....................... 17      17
mem_a<9>             X.............X..........X.............. 3       3
mem_a<5>             X.........X...........X................. 3       3
address<13>          XXXXX.XXXXXXXXXXX....................... 16      16
address<12>          XXXX..XXXXXXXXXXX....................... 15      15
mem_a<6>             X..........X...........X................ 3       3
address<11>          XXX...XXXXXXXXXXX....................... 14      14
mem_a<8>             X............X..........X............... 3       3
address<10>          XX....XXXXXXXXXXX....................... 13      13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

 "mem_a<13>"  =  rst * "saddress<13>"
	+ /rst * "address<13>"    

 "mem_a<12>"  =  rst * "saddress<12>"
	+ /rst * "address<12>"    

 "mem_a<11>"  =  rst * "saddress<11>"
	+ /rst * "address<11>"    

 "mem_a<10>"  =  rst * "saddress<10>"
	+ /rst * "address<10>"    

 "mem_a<9>"  =  rst * "saddress<9>"
	+ /rst * "address<9>.FBK".LFBK    

 "mem_a<8>"  =  rst * "saddress<8>"
	+ /rst * "address<8>.FBK".LFBK    

 "mem_a<7>"  =  rst * "saddress<7>"
	+ /rst * "address<7>.FBK".LFBK    

 "mem_a<6>"  =  rst * "saddress<6>"
	+ /rst * "address<6>"    

 "mem_a<14>"  =  rst * "saddress<14>"
	+ /rst * "address<14>"    

 "mem_a<5>"  =  rst * "saddress<5>"
	+ /rst * "address<5>"    

 "mem_a<4>"  =  rst * "saddress<4>"
	+ /rst * "address<4>"    

 "mem_a<3>"  =  rst * "saddress<3>"
	+ /rst * "address<3>"    

 "mem_a<2>"  =  rst * "saddress<2>"
	+ /rst * "address<2>"    

 "mem_a<1>"  =  rst * "saddress<1>"
	+ /rst * "address<1>"    

 "mem_a<0>"  =  rst * "saddress<0>"
	+ /rst * "address<0>"    

/mem_wr  =  /rst * "current_state<3>.FBK".LFBK    

 mem_rd  =  /rst    

/oe  =  /"current_state<3>" * /"current_state<4>"    

 clock  =  clk    

 datao  :=  load * "mem_d<7>".PIN
	+ /load * "sbuf<6>"
    datao.CLKF  =  clko
    datao.PRLD  =  GND    

 "mem_d<0>"  =  "din<0>"
    "mem_d<0>".TRST  =  "N_din<7>$BUF0/N_din<7>$BUF0_TRST"    

 "mem_d<1>"  =  "din<1>"
    "mem_d<1>".TRST  =  "N_din<7>$BUF0/N_din<7>$BUF0_TRST"    

 "mem_d<2>"  =  "din<2>"
    "mem_d<2>".TRST  =  "N_din<7>$BUF0/N_din<7>$BUF0_TRST"    

 "mem_d<3>"  =  "din<3>"
    "mem_d<3>".TRST  =  "N_din<7>$BUF0/N_din<7>$BUF0_TRST.FBK".LFBK    

 "mem_d<4>"  =  "din<4>"
    "mem_d<4>".TRST  =  "N_din<7>$BUF0/N_din<7>$BUF0_TRST"    

 "mem_d<5>"  =  "din<5>"
    "mem_d<5>".TRST  =  "N_din<7>$BUF0/N_din<7>$BUF0_TRST.FBK".LFBK    

 "mem_d<6>"  =  "din<6>"
    "mem_d<6>".TRST  =  "N_din<7>$BUF0/N_din<7>$BUF0_TRST.FBK".LFBK    

 "mem_d<7>"  =  "din<7>"
    "mem_d<7>".TRST  =  "N_din<7>$BUF0/N_din<7>$BUF0_TRST.FBK".LFBK    

 "N_din<7>$BUF0/N_din<7>$BUF0_TRST"  =  /rst * "current_state<3>.FBK".LFBK
	+ /rst * "current_state<4>.FBK".LFBK    

 mem_f  :=  Vcc
    mem_f.CLKF  =  /"address<14>"
    mem_f.RSTF  =  rst
    mem_f.PRLD  =  GND    

/"address<0>".T  =  mem_f.PIN
    "address<0>".CLKF  =  /"current_state<3>.FBK".LFBK
    "address<0>".RSTF  =  rst
    "address<0>".PRLD  =  GND    

 "address<10>".T  =  "address<0>" * "address<1>" * "address<3>" * 
	"address<5>" * "address<7>" * "address<2>" * "address<4>" * 
	"address<6>" * "address<9>.FBK".LFBK * "address<8>.FBK".LFBK * 
	/mem_f.PIN
    "address<10>".CLKF  =  /"current_state<3>"
    "address<10>".RSTF  =  rst
    "address<10>".PRLD  =  GND    

 "address<11>".T  =  "address<0>" * "address<1>" * "address<3>" * 
	"address<5>" * "address<7>" * "address<2>" * "address<4>" * 
	"address<6>" * "address<9>.FBK".LFBK * "address<10>.FBK".LFBK * 
	"address<8>.FBK".LFBK * /mem_f.PIN
    "address<11>".CLKF  =  /"current_state<3>"
    "address<11>".RSTF  =  rst
    "address<11>".PRLD  =  GND    

 "address<12>".T  =  "address<0>" * "address<1>" * "address<3>" * 
	"address<5>" * "address<7>" * "address<2>" * "address<4>" * 
	"address<6>" * "address<9>.FBK".LFBK * "address<10>.FBK".LFBK * 
	"address<8>.FBK".LFBK * "address<11>.FBK".LFBK * /mem_f.PIN
    "address<12>".CLKF  =  /"current_state<3>"
    "address<12>".RSTF  =  rst
    "address<12>".PRLD  =  GND    

 "address<13>".T  =  "address<0>" * "address<1>" * "address<3>" * 
	"address<5>" * "address<7>" * "address<2>" * "address<4>" * 
	"address<6>" * "address<9>.FBK".LFBK * "address<10>.FBK".LFBK * 
	"address<8>.FBK".LFBK * "address<11>.FBK".LFBK * "address<12>.FBK".LFBK * 
	/mem_f.PIN
    "address<13>".CLKF  =  /"current_state<3>"
    "address<13>".RSTF  =  rst
    "address<13>".PRLD  =  GND    

 "address<14>".T  =  "address<0>" * "address<1>" * "address<3>" * 
	"address<5>" * "address<7>" * "address<2>" * "address<4>" * 
	"address<6>" * "address<9>.FBK".LFBK * "address<10>.FBK".LFBK * 
	"address<8>.FBK".LFBK * "address<11>.FBK".LFBK * "address<12>.FBK".LFBK * 
	"address<13>.FBK".LFBK * /mem_f.PIN
    "address<14>".CLKF  =  /"current_state<3>"
    "address<14>".RSTF  =  rst
    "address<14>".PRLD  =  GND    

 "address<1>".T  =  "address<0>.FBK".LFBK * /mem_f.PIN
    "address<1>".CLKF  =  /"current_state<3>.FBK".LFBK
    "address<1>".RSTF  =  rst
    "address<1>".PRLD  =  GND    

 "address<2>".T  =  "address<0>" * "address<1>" * /mem_f.PIN
    "address<2>".CLKF  =  /"current_state<3>"
    "address<2>".RSTF  =  rst
    "address<2>".PRLD  =  GND    

 "address<3>".T  =  "address<0>" * "address<1>" * 
	"address<2>.FBK".LFBK * /mem_f.PIN
    "address<3>".CLKF  =  /"current_state<3>"
    "address<3>".RSTF  =  rst
    "address<3>".PRLD  =  GND    

 "address<4>".T  =  "address<0>" * "address<1>" * 
	"address<2>.FBK".LFBK * "address<3>.FBK".LFBK * /mem_f.PIN
    "address<4>".CLKF  =  /"current_state<3>"
    "address<4>".RSTF  =  rst
    "address<4>".PRLD  =  GND    

 "address<5>".T  =  "address<0>" * "address<1>" * 
	"address<2>.FBK".LFBK * "address<3>.FBK".LFBK * "address<4>.FBK".LFBK * 
	/mem_f.PIN
    "address<5>".CLKF  =  /"current_state<3>"
    "address<5>".RSTF  =  rst
    "address<5>".PRLD  =  GND    

 "address<6>".T  =  "address<0>" * "address<1>" * 
	"address<2>.FBK".LFBK * "address<3>.FBK".LFBK * "address<4>.FBK".LFBK * 
	"address<5>.FBK".LFBK * /mem_f.PIN