ex24.rpt
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 961 行 · 第 1/4 页
RPT
961 行
2: "din<3>" 9: "mem_d<0>".PIN 16: "current_state<3>.FBK".LFBK
3: "din<5>" 10: "mem_d<1>".PIN 17: "current_state<4>.FBK".LFBK
4: "din<6>" 11: "mem_d<7>".PIN 18: mem_f.PIN
5: "din<7>" 12: rst 19: "sbuf<0>.FBK".LFBK
6: "N_din<7>$BUF0/N_din<7>$BUF0_TRST.FBK".LFBK
13: "address<0>.FBK".LFBK
20: "sbuf<6>"
7: eoc 14: "current_state<0>.FBK".LFBK
21: start.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
mem_d<3> .X...X.................................. 2 2
mem_d<5> ..X..X.................................. 2 2
N_din<7>$BUF0/N_din<7>$BUF0_TRST
...........X...XX....................... 3 3
sbuf<1> X......X.X........X..................... 4 4
sbuf<0> X......XX.........X..................... 4 4
mem_d<6> ...X.X.................................. 2 2
mem_d<7> ....XX.................................. 2 2
current_state<4> ...........X...XXX...................... 4 4
mem_wr ...........X...X........................ 2 2
mem_rd ...........X............................ 1 1
current_state<3> ......X....X..XX.X...................... 5 5
datao X......X..X........X.................... 4 4
current_state<2> ......X....X..X..X..X................... 5 5
current_state<0> ...........X.X..XX...................... 4 4
address<1> ...........XX..X.X...................... 4 4
address<0> ...........X...X.X...................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 28/8
Number of signals used by logic mapping into function block: 28
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 14 I/O
oe 1 0 0 4 FB3_3 STD 15 I/O O
saddress<2> 2 0 0 3 FB3_4 STD (b) (b)
saddress<1> 2 0 0 3 FB3_5 STD 17 I/O (b)
saddress<14> 2 0 0 3 FB3_6 STD 18 I/O I
saddress<13> 2 0 0 3 FB3_7 STD (b) (b)
start 3 0 0 2 FB3_8 STD 19 I/O I/O
saddress<12> 2 0 0 3 FB3_9 STD 20 I/O (b)
saddress<11> 2 0 0 3 FB3_10 STD (b) (b)
clock 1 0 0 4 FB3_11 STD 21 I/O O
saddress<10> 2 0 0 3 FB3_12 STD 23 I/O (b)
saddress<0> 2 0 0 3 FB3_13 STD (b) (b)
sbuf<6> 3 0 0 2 FB3_14 STD 24 I/O (b)
sbuf<5> 3 0 0 2 FB3_15 STD 25 I/O (b)
sbuf<4> 3 0 0 2 FB3_16 STD 26 I/O (b)
sbuf<3> 3 0 0 2 FB3_17 STD 31 I/O (b)
sbuf<2> 3 0 0 2 FB3_18 STD (b) (b)
Signals Used by Logic in Function Block
1: clk 11: rst 20: "saddress<12>.FBK".LFBK
2: clki 12: "current_state<0>"
21: "saddress<13>.FBK".LFBK
3: clko 13: "current_state<1>.FBK".LFBK
22: "saddress<1>.FBK".LFBK
4: datai 14: "current_state<3>"
23: "saddress<9>"
5: load 15: "current_state<4>"
24: "sbuf<1>"
6: "mem_d<2>".PIN 16: mem_f.PIN 25: "sbuf<2>.FBK".LFBK
7: "mem_d<3>".PIN 17: "saddress<0>.FBK".LFBK
26: "sbuf<3>.FBK".LFBK
8: "mem_d<4>".PIN 18: "saddress<10>.FBK".LFBK
27: "sbuf<4>.FBK".LFBK
9: "mem_d<5>".PIN 19: "saddress<11>.FBK".LFBK
28: "sbuf<5>.FBK".LFBK
10: "mem_d<6>".PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
oe .............XX......................... 2 2
saddress<2> .X...................X.................. 2 2
saddress<1> .X..............X....................... 2 2
saddress<14> .X..................X................... 2 2
saddress<13> .X.................X.................... 2 2
start ..........XXX..X........................ 4 4
saddress<12> .X................X..................... 2 2
saddress<11> .X...............X...................... 2 2
clock X....................................... 1 1
saddress<10> .X....................X................. 2 2
saddress<0> .X.X.................................... 2 2
sbuf<6> ..X.X....X.................X............ 4 4
sbuf<5> ..X.X...X.................X............. 4 4
sbuf<4> ..X.X..X.................X.............. 4 4
sbuf<3> ..X.X.X.................X............... 4 4
sbuf<2> ..X.XX.................X................ 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 27/9
Number of signals used by logic mapping into function block: 27
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
mem_a<7> 2 0 0 3 FB4_2 STD 57 I/O O
mem_a<10> 2 0 0 3 FB4_3 STD 58 I/O O
(unused) 0 0 0 5 FB4_4 (b)
mem_a<11> 2 0 0 3 FB4_5 STD 61 I/O O
mem_a<13> 2 0 0 3 FB4_6 STD 62 I/O O
address<7> 3 0 0 2 FB4_7 STD (b) (b)
mem_a<12> 2 0 0 3 FB4_8 STD 63 I/O O
mem_a<14> 2 0 0 3 FB4_9 STD 65 I/O O
address<6> 3 0 0 2 FB4_10 STD (b) (b)
mem_d<0> 2 0 0 3 FB4_11 STD 66 I/O I/O
address<5> 3 0 0 2 FB4_12 STD 67 I/O (b)
address<4> 3 0 0 2 FB4_13 STD (b) (b)
mem_d<2> 2 0 0 3 FB4_14 STD 68 I/O I/O
mem_d<1> 2 0 0 3 FB4_15 STD 69 I/O I/O
address<3> 3 0 0 2 FB4_16 STD (b) (b)
mem_d<4> 2 0 0 3 FB4_17 STD 70 I/O I/O
address<2> 3 0 0 2 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "din<0>" 10: "address<12>" 19: "address<7>.FBK".LFBK
2: "din<1>" 11: "address<13>" 20: "current_state<3>"
3: "din<2>" 12: "address<14>" 21: mem_f.PIN
4: "din<4>" 13: "address<1>" 22: "saddress<10>"
5: "N_din<7>$BUF0/N_din<7>$BUF0_TRST"
14: "address<2>.FBK".LFBK
23: "saddress<11>"
6: rst 15: "address<3>.FBK".LFBK
24: "saddress<12>"
7: "address<0>" 16: "address<4>.FBK".LFBK
25: "saddress<13>"
8: "address<10>" 17: "address<5>.FBK".LFBK
26: "saddress<14>"
9: "address<11>" 18: "address<6>.FBK".LFBK
27: "saddress<7>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
mem_a<7> .....X............X.......X............. 3 3
mem_a<10> .....X.X.............X.................. 3 3
mem_a<11> .....X..X.............X................. 3 3
mem_a<13> .....X....X.............X............... 3 3
address<7> .....XX.....XXXXXX.XX................... 10 10
mem_a<12> .....X...X.............X................ 3 3
mem_a<14> .....X.....X.............X.............. 3 3
address<6> .....XX.....XXXXX..XX................... 9 9
mem_d<0> X...X................................... 2 2
address<5> .....XX.....XXXX...XX................... 8 8
address<4> .....XX.....XXX....XX................... 7 7
mem_d<2> ..X.X................................... 2 2
mem_d<1> .X..X................................... 2 2
address<3> .....XX.....XX.....XX................... 6 6
mem_d<4> ...XX................................... 2 2
address<2> .....XX.....X......XX................... 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 32 I/O
(unused) 0 0 0 5 FB5_3 33 I/O I
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 34 I/O
(unused) 0 0 0 5 FB5_6 35 I/O I
(unused) 0 0 0 5 FB5_7 (b)
(unused) 0 0 0 5 FB5_8 36 I/O I
(unused) 0 0 0 5 FB5_9 37 I/O I
(unused) 0 0 0 5 FB5_10 (b)
(unused) 0 0 0 5 FB5_11 39 I/O I
(unused) 0 0 0 5 FB5_12 40 I/O I
(unused) 0 0 0 5 FB5_13 (b)
(unused) 0 0 0 5 FB5_14 41 I/O I
(unused) 0 0 0 5 FB5_15 43 I/O I
(unused) 0 0 0 5 FB5_16 (b)
(unused) 0 0 0 5 FB5_17 44 I/O
(unused) 0 0 0 5 FB5_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 26/10
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB6_1 (b)
mem_a<0> 2 0 0 3 FB6_2 STD 45 I/O O
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