ex24.rpt
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RPT
961 行
cpldfit: version E.38 Xilinx Inc.
Fitter Report
Design Name: ex24 Date: 3-12-2008, 9:15AM
Device Used: XC95108-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
72 /108 ( 66%) 168 /540 ( 31%) 44 /108 ( 40%) 45 /69 ( 65%) 112/216 ( 51%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 14 14 | I/O : 42 21
Output : 20 20 | GCK/IO : 1 2
Bidirectional : 10 10 | GTS/IO : 2 0
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 45 45
MACROCELL RESOURCES:
Total Macrocells Available 108
Registered Macrocells 44
Non-registered Macrocell driving I/O 27
GLOBAL RESOURCES:
Signal 'clk' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 72 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 72 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
N_din<7>$BUF0/N_din<7>$BUF0_TRST 2 3 FB2_5 STD 74 GSR/I/O (b)
address<0> 3 3 FB2_18 STD (b) (b)
address<10> 3 13 FB6_18 STD (b) (b)
address<11> 3 14 FB6_16 STD (b) (b)
address<12> 3 15 FB6_14 STD 54 I/O (b)
address<13> 3 16 FB6_13 STD (b) (b)
address<14> 3 17 FB6_10 STD (b) (b)
address<1> 3 4 FB2_17 STD 84 I/O I
address<2> 3 5 FB4_18 STD (b) (b)
address<3> 3 6 FB4_16 STD (b) (b)
address<4> 3 7 FB4_13 STD (b) (b)
address<5> 3 8 FB4_12 STD 67 I/O (b)
address<6> 3 9 FB4_10 STD (b) (b)
address<7> 3 10 FB4_7 STD (b) (b)
address<8> 3 11 FB6_8 STD 50 I/O (b)
address<9> 3 12 FB6_7 STD (b) (b)
clock 1 1 FB3_11 STD FAST 21 I/O O
current_state<0> 3 4 FB2_16 STD 83 I/O I
current_state<2> 3 5 FB2_15 STD 82 I/O I
current_state<3> 3 5 FB2_13 STD (b) (b)
current_state<4> 3 4 FB2_10 STD (b) (b)
datao 3 4 FB2_14 STD FAST 81 I/O O
mem_a<0> 2 3 FB6_2 STD FAST 45 I/O O
mem_a<10> 2 3 FB4_3 STD FAST 58 I/O O
mem_a<11> 2 3 FB4_5 STD FAST 61 I/O O
mem_a<12> 2 3 FB4_8 STD FAST 63 I/O O
mem_a<13> 2 3 FB4_6 STD FAST 62 I/O O
mem_a<14> 2 3 FB4_9 STD FAST 65 I/O O
mem_a<1> 2 3 FB6_3 STD FAST 46 I/O O
mem_a<2> 2 3 FB6_5 STD FAST 47 I/O O
mem_a<3> 2 3 FB6_6 STD FAST 48 I/O O
mem_a<4> 2 3 FB6_9 STD FAST 51 I/O O
mem_a<5> 2 3 FB6_12 STD FAST 53 I/O O
mem_a<6> 2 3 FB6_15 STD FAST 55 I/O O
mem_a<7> 2 3 FB4_2 STD FAST 57 I/O O
mem_a<8> 2 3 FB6_17 STD FAST 56 I/O O
mem_a<9> 2 3 FB6_11 STD FAST 52 I/O O
mem_d<0> 2 2 FB4_11 STD FAST 66 I/O I/O
mem_d<1> 2 2 FB4_15 STD FAST 69 I/O I/O
mem_d<2> 2 2 FB4_14 STD FAST 68 I/O I/O
mem_d<3> 2 2 FB2_2 STD FAST 71 I/O I/O
mem_d<4> 2 2 FB4_17 STD FAST 70 I/O I/O
mem_d<5> 2 2 FB2_3 STD FAST 72 I/O I/O
mem_d<6> 2 2 FB2_8 STD FAST 76 GTS/I/O I/O
mem_d<7> 2 2 FB2_9 STD FAST 77 GTS/I/O I/O
mem_f 2 2 FB1_5 STD FAST 3 I/O I/O
mem_rd 1 1 FB2_12 STD FAST 80 I/O O
mem_wr 1 2 FB2_11 STD FAST 79 I/O O
oe 1 2 FB3_3 STD FAST 15 I/O O
saddress<0> 2 2 FB3_13 STD (b) (b)
saddress<10> 2 2 FB3_12 STD 23 I/O (b)
saddress<11> 2 2 FB3_10 STD (b) (b)
saddress<12> 2 2 FB3_9 STD 20 I/O (b)
saddress<13> 2 2 FB3_7 STD (b) (b)
saddress<14> 2 2 FB3_6 STD 18 I/O I
saddress<1> 2 2 FB3_5 STD 17 I/O (b)
saddress<2> 2 2 FB3_4 STD (b) (b)
saddress<3> 2 2 FB1_18 STD (b) (b)
saddress<4> 2 2 FB1_17 STD 13 I/O (b)
saddress<5> 2 2 FB1_16 STD 12 GCK/I/O (b)
saddress<6> 2 2 FB1_15 STD 11 I/O (b)
saddress<7> 2 2 FB1_14 STD 10 GCK/I/O GCK/I
saddress<8> 2 2 FB1_13 STD (b) (b)
saddress<9> 2 2 FB1_12 STD 9 GCK/I/O (b)
sbuf<0> 3 4 FB2_7 STD (b) (b)
sbuf<1> 3 4 FB2_6 STD 75 I/O (b)
sbuf<2> 3 4 FB3_18 STD (b) (b)
sbuf<3> 3 4 FB3_17 STD 31 I/O (b)
sbuf<4> 3 4 FB3_16 STD 26 I/O (b)
sbuf<5> 3 4 FB3_15 STD 25 I/O (b)
sbuf<6> 3 4 FB3_14 STD 24 I/O (b)
start 3 4 FB3_8 STD FAST 19 I/O I/O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk FB1_14 10 GCK/I/O GCK/I
clki FB2_17 84 I/O I
clko FB2_16 83 I/O I
datai FB2_15 82 I/O I
din<0> FB5_8 36 I/O I
din<1> FB5_3 33 I/O I
din<2> FB5_6 35 I/O I
din<3> FB5_9 37 I/O I
din<4> FB5_12 40 I/O I
din<5> FB5_11 39 I/O I
din<6> FB5_14 41 I/O I
din<7> FB5_15 43 I/O I
eoc FB3_6 18 I/O I
load FB1_3 2 I/O I
rst FB1_6 4 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 8 10 10 16 0/1 12
FB2 16 21 21 39 3/4 12
FB3 16 28 28 36 2/1 12
FB4 16 27 27 38 6/4 11
FB5 0 0 0 0 0/0 11
FB6 16 26 26 39 9/0 11
---- ----- ----- -----
72 168 20/10 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 10/26
Number of signals used by logic mapping into function block: 10
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 1 I/O
(unused) 0 0 0 5 FB1_3 2 I/O I
(unused) 0 0 0 5 FB1_4 (b)
mem_f 2 0 0 3 FB1_5 STD 3 I/O I/O
(unused) 0 0 0 5 FB1_6 4 I/O I
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 5 I/O
(unused) 0 0 0 5 FB1_9 6 I/O
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 0 5 FB1_11 7 I/O
saddress<9> 2 0 0 3 FB1_12 STD 9 GCK/I/O (b)
saddress<8> 2 0 0 3 FB1_13 STD (b) (b)
saddress<7> 2 0 0 3 FB1_14 STD 10 GCK/I/O GCK/I
saddress<6> 2 0 0 3 FB1_15 STD 11 I/O (b)
saddress<5> 2 0 0 3 FB1_16 STD 12 GCK/I/O (b)
saddress<4> 2 0 0 3 FB1_17 STD 13 I/O (b)
saddress<3> 2 0 0 3 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: clki 5: "saddress<3>.FBK".LFBK
8: "saddress<6>.FBK".LFBK
2: rst 6: "saddress<4>.FBK".LFBK
9: "saddress<7>.FBK".LFBK
3: "address<14>" 7: "saddress<5>.FBK".LFBK
10: "saddress<8>.FBK".LFBK
4: "saddress<2>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
mem_f .XX..................................... 2 2
saddress<9> X........X.............................. 2 2
saddress<8> X.......X............................... 2 2
saddress<7> X......X................................ 2 2
saddress<6> X.....X................................. 2 2
saddress<5> X....X.................................. 2 2
saddress<4> X...X................................... 2 2
saddress<3> X..X.................................... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 21/15
Number of signals used by logic mapping into function block: 21
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
mem_d<3> 2 0 0 3 FB2_2 STD 71 I/O I/O
mem_d<5> 2 0 0 3 FB2_3 STD 72 I/O I/O
(unused) 0 0 0 5 FB2_4 (b)
N_din<7>$BUF0/N_din<7>$BUF0_TRST
2 0 0 3 FB2_5 STD 74 GSR/I/O (b)
sbuf<1> 3 0 0 2 FB2_6 STD 75 I/O (b)
sbuf<0> 3 0 0 2 FB2_7 STD (b) (b)
mem_d<6> 2 0 0 3 FB2_8 STD 76 GTS/I/O I/O
mem_d<7> 2 0 0 3 FB2_9 STD 77 GTS/I/O I/O
current_state<4> 3 0 0 2 FB2_10 STD (b) (b)
mem_wr 1 0 0 4 FB2_11 STD 79 I/O O
mem_rd 1 0 0 4 FB2_12 STD 80 I/O O
current_state<3> 3 0 0 2 FB2_13 STD (b) (b)
datao 3 0 0 2 FB2_14 STD 81 I/O O
current_state<2> 3 0 0 2 FB2_15 STD 82 I/O I
current_state<0> 3 0 0 2 FB2_16 STD 83 I/O I
address<1> 3 0 0 2 FB2_17 STD 84 I/O I
address<0> 3 0 0 2 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: clko 8: load 15: "current_state<2>.FBK".LFBK
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