ex5.out

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· OUT 代码 · 共 18 行

Reading in the Synopsys vhdl primitives.

Inferred memory devices in process 
	in routine EX5 line 14 in file
         'D:/temp/eda6000/xc95/ex5/ex5.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      sout_reg       | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

sout_reg (width 8)
------------------
    set/reset/toggle: none


Writing to hnl file 'd:\temp\EDA6000\XC95\EX5\ex5/workdirs/WORK/EX5.hnl'