ex5.mod

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MOD 代码 · 共 32 行

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex5";

/* port names and type */
INPUT S:PIN20 = sin;
INPUT S:PIN23 = clk;
OUTPUT S:PIN66 = sout<0>;
OUTPUT S:PIN69 = sout<1>;
OUTPUT S:PIN68 = sout<2>;
OUTPUT S:PIN71 = sout<3>;
OUTPUT S:PIN70 = sout<4>;
OUTPUT S:PIN72 = sout<5>;
OUTPUT S:PIN76 = sout<6>;
OUTPUT S:PIN77 = sout<7>;

/* timing arc definitions */
clk_sout<0>_delay: DELAY clk sout<0>;
clk_sout<1>_delay: DELAY clk sout<1>;
clk_sout<2>_delay: DELAY clk sout<2>;
clk_sout<3>_delay: DELAY clk sout<3>;
clk_sout<4>_delay: DELAY clk sout<4>;
clk_sout<5>_delay: DELAY clk sout<5>;
clk_sout<6>_delay: DELAY clk sout<6>;
clk_sout<7>_delay: DELAY clk sout<7>;

/* timing check arc definitions */
sin_clk_setup: SETUP(POSEDGE) sin clk;
sin_clk_hold: HOLD(POSEDGE) sin clk;

ENDMODEL