ex5.tim

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                           Performance Summary Report
                           --------------------------

Design:     ex5
Device:     XC9572-7-PC84
Speed File: Version 3.0
Program:    Timing Report Generator:  version E.38
Date:       Tue Mar 11 23:18:22 2008

Performance Summary: 

Clock net 'clk' path delays:

Clock Pad to Output Pad (tCO)             :          8.5ns (1 macrocell levels)
Clock Pad 'clk' to Output Pad 'sout<0>'                           (Pterm Clock)

Clock to Setup (tCYC)                     :          9.0ns (1 macrocell levels)
Clock to Q, net 'sout<0>.Q' to DFF Setup(D) at 'sout<1>.D'        (Pterm Clock)
Target FF drives output net 'N_sout<1>$Q'

Setup to Clock at the Pad (tSU)           :          0.5ns (0 macrocell levels)
Data signal 'sin' to DFF D input Pin at 'sout<0>.D'
Clock pad 'clk'                                                   (Pterm Clock)

                          Minimum Clock Period: 10.0ns
                     Maximum Internal Clock Speed: 100.0Mhz
                         (Limited by Clock Pulse Width)

--------------------------------------------------------------------------------
                      Clock Pad to Output Pad (tCO) (nsec)

\ From      c
 \          l
  \         k
   \         
    \        
     \       
      \      
  To   \------

sout<0>   8.5
sout<1>   8.5
sout<2>   8.5
sout<3>   8.5
sout<4>   8.5
sout<5>   8.5
sout<6>   8.5
sout<7>   8.5

--------------------------------------------------------------------------------
                       Setup to Clock at Pad (tSU) (nsec)

\ From      c
 \          l
  \         k
   \         
    \        
     \       
      \      
  To   \------

sin       0.5

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                  (Clock: clk)

\ From        s     s     s     s     s     s     s
 \            o     o     o     o     o     o     o
  \           u     u     u     u     u     u     u
   \          t     t     t     t     t     t     t
    \         <     <     <     <     <     <     <
     \        0     1     2     3     4     5     6
      \       >     >     >     >     >     >     >
       \      .     .     .     .     .     .     .
        \     Q     Q     Q     Q     Q     Q     Q
  To     \------------------------------------------

sout<1>.D   9.0                                    
sout<2>.D         8.0                              
sout<3>.D               8.0                        
sout<4>.D                     8.0                  
sout<5>.D                           8.0            
sout<6>.D                                 8.0      
sout<7>.D                                       8.0

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU) -             Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and end at register D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.