time_sim.edn
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 1,355 行 · 第 1/4 页
EDN
1,355 行
) (net N_sout_3__D (joined (portRef IN (instanceRef N_sout_3__REG)) (portRef OUT (instanceRef N_sout_3__XOR)) ) ) (net N_sout_3__CLKF (joined (portRef CLK (instanceRef N_sout_3__REG)) (portRef OUT (instanceRef N_sout_3__CLKF_36)) ) ) (net N_sout_3__CLKF_PT_0 (joined (portRef OUT (instanceRef N_sout_3__CLKF_PT_0_35)) (portRef IN0 (instanceRef N_sout_3__CLKF_36)) (portRef IN1 (instanceRef N_sout_3__CLKF_36)) ) ) (net N_sout_3__D1 (joined (portRef OUT (instanceRef N_sout_3__D1_37)) (portRef IN0 (instanceRef N_sout_3__XOR)) ) ) (net N_sout_3__D2_PT_0 (joined (portRef OUT (instanceRef N_sout_3__D2_PT_0_38)) (portRef IN0 (instanceRef N_sout_3__D2_39)) (portRef IN1 (instanceRef N_sout_3__D2_39)) ) ) (net N_sout_3__D2 (joined (portRef OUT (instanceRef N_sout_3__D2_39)) (portRef IN1 (instanceRef N_sout_3__XOR)) ) ) (net N_sout_3__FBK (joined (portRef OUT (instanceRef N_sout_3__FBK_40)) (portRef IN0 (instanceRef N_sout_4__D2_PT_0_46)) (portRef IN1 (instanceRef N_sout_4__D2_PT_0_46)) ) ) (net N_sout_4__Q (joined (portRef IN (instanceRef sout_4___41)) (portRef OUT (instanceRef N_sout_4__Q_42)) ) ) (net N_sout_4__Q_4 (joined (portRef IN (instanceRef N_sout_4__Q_42)) (portRef OUT (instanceRef N_sout_4__REG)) (portRef IN (instanceRef N_sout_4__FBK_48)) ) ) (net N_sout_4__D (joined (portRef IN (instanceRef N_sout_4__REG)) (portRef OUT (instanceRef N_sout_4__XOR)) ) ) (net N_sout_4__CLKF (joined (portRef CLK (instanceRef N_sout_4__REG)) (portRef OUT (instanceRef N_sout_4__CLKF_44)) ) ) (net N_sout_4__CLKF_PT_0 (joined (portRef OUT (instanceRef N_sout_4__CLKF_PT_0_43)) (portRef IN0 (instanceRef N_sout_4__CLKF_44)) (portRef IN1 (instanceRef N_sout_4__CLKF_44)) ) ) (net N_sout_4__D1 (joined (portRef OUT (instanceRef N_sout_4__D1_45)) (portRef IN0 (instanceRef N_sout_4__XOR)) ) ) (net N_sout_4__D2_PT_0 (joined (portRef OUT (instanceRef N_sout_4__D2_PT_0_46)) (portRef IN0 (instanceRef N_sout_4__D2_47)) (portRef IN1 (instanceRef N_sout_4__D2_47)) ) ) (net N_sout_4__D2 (joined (portRef OUT (instanceRef N_sout_4__D2_47)) (portRef IN1 (instanceRef N_sout_4__XOR)) ) ) (net N_sout_4__FBK (joined (portRef OUT (instanceRef N_sout_4__FBK_48)) (portRef IN0 (instanceRef N_sout_5__D2_PT_0_54)) (portRef IN1 (instanceRef N_sout_5__D2_PT_0_54)) ) ) (net N_sout_5__Q (joined (portRef IN (instanceRef sout_5___49)) (portRef OUT (instanceRef N_sout_5__Q_50)) ) ) (net N_sout_5__Q_5 (joined (portRef IN (instanceRef N_sout_5__Q_50)) (portRef OUT (instanceRef N_sout_5__REG)) (portRef IN (instanceRef N_sout_5__FBK_56)) ) ) (net N_sout_5__D (joined (portRef IN (instanceRef N_sout_5__REG)) (portRef OUT (instanceRef N_sout_5__XOR)) ) ) (net N_sout_5__CLKF (joined (portRef CLK (instanceRef N_sout_5__REG)) (portRef OUT (instanceRef N_sout_5__CLKF_52)) ) ) (net N_sout_5__CLKF_PT_0 (joined (portRef OUT (instanceRef N_sout_5__CLKF_PT_0_51)) (portRef IN0 (instanceRef N_sout_5__CLKF_52)) (portRef IN1 (instanceRef N_sout_5__CLKF_52)) ) ) (net N_sout_5__D1 (joined (portRef OUT (instanceRef N_sout_5__D1_53)) (portRef IN0 (instanceRef N_sout_5__XOR)) ) ) (net N_sout_5__D2_PT_0 (joined (portRef OUT (instanceRef N_sout_5__D2_PT_0_54)) (portRef IN0 (instanceRef N_sout_5__D2_55)) (portRef IN1 (instanceRef N_sout_5__D2_55)) ) ) (net N_sout_5__D2 (joined (portRef OUT (instanceRef N_sout_5__D2_55)) (portRef IN1 (instanceRef N_sout_5__XOR)) ) ) (net N_sout_5__FBK (joined (portRef OUT (instanceRef N_sout_5__FBK_56)) (portRef IN0 (instanceRef N_sout_6__D2_PT_0_62)) (portRef IN1 (instanceRef N_sout_6__D2_PT_0_62)) ) ) (net N_sout_6__Q (joined (portRef IN (instanceRef sout_6___57)) (portRef OUT (instanceRef N_sout_6__Q_58)) ) ) (net N_sout_6__Q_6 (joined (portRef IN (instanceRef N_sout_6__Q_58)) (portRef OUT (instanceRef N_sout_6__REG)) (portRef IN (instanceRef N_sout_6__FBK_64)) ) ) (net N_sout_6__D (joined (portRef IN (instanceRef N_sout_6__REG)) (portRef OUT (instanceRef N_sout_6__XOR)) ) ) (net N_sout_6__CLKF (joined (portRef CLK (instanceRef N_sout_6__REG)) (portRef OUT (instanceRef N_sout_6__CLKF_60)) ) ) (net N_sout_6__CLKF_PT_0 (joined (portRef OUT (instanceRef N_sout_6__CLKF_PT_0_59)) (portRef IN0 (instanceRef N_sout_6__CLKF_60)) (portRef IN1 (instanceRef N_sout_6__CLKF_60)) ) ) (net N_sout_6__D1 (joined (portRef OUT (instanceRef N_sout_6__D1_61)) (portRef IN0 (instanceRef N_sout_6__XOR)) ) ) (net N_sout_6__D2_PT_0 (joined (portRef OUT (instanceRef N_sout_6__D2_PT_0_62)) (portRef IN0 (instanceRef N_sout_6__D2_63)) (portRef IN1 (instanceRef N_sout_6__D2_63)) ) ) (net N_sout_6__D2 (joined (portRef OUT (instanceRef N_sout_6__D2_63)) (portRef IN1 (instanceRef N_sout_6__XOR)) ) ) (net N_sout_6__FBK (joined (portRef OUT (instanceRef N_sout_6__FBK_64)) (portRef IN0 (instanceRef N_sout_7__D2_PT_0_70)) (portRef IN1 (instanceRef N_sout_7__D2_PT_0_70)) ) ) (net (rename N_sout_7__ "N_sout<7>") (joined (portRef IN (instanceRef sout_7___65)) (portRef OUT (instanceRef N_sout_7___66)) ) ) (net N_sout_7__Q (joined (portRef IN (instanceRef N_sout_7___66)) (portRef OUT (instanceRef N_sout_7__REG)) ) ) (net N_sout_7__D (joined (portRef IN (instanceRef N_sout_7__REG)) (portRef OUT (instanceRef N_sout_7__XOR)) ) ) (net N_sout_7__CLKF (joined (portRef CLK (instanceRef N_sout_7__REG)) (portRef OUT (instanceRef N_sout_7__CLKF_68)) ) ) (net N_sout_7__CLKF_PT_0 (joined (portRef OUT (instanceRef N_sout_7__CLKF_PT_0_67)) (portRef IN0 (instanceRef N_sout_7__CLKF_68)) (portRef IN1 (instanceRef N_sout_7__CLKF_68)) ) ) (net N_sout_7__D1 (joined (portRef OUT (instanceRef N_sout_7__D1_69)) (portRef IN0 (instanceRef N_sout_7__XOR)) ) ) (net N_sout_7__D2_PT_0 (joined (portRef OUT (instanceRef N_sout_7__D2_PT_0_70)) (portRef IN0 (instanceRef N_sout_7__D2_71)) (portRef IN1 (instanceRef N_sout_7__D2_71)) ) ) (net N_sout_7__D2 (joined (portRef OUT (instanceRef N_sout_7__D2_71)) (portRef IN1 (instanceRef N_sout_7__XOR)) ) ) (net VCC (joined (portRef CE (instanceRef N_sout_0__REG)) (portRef OUT (instanceRef VCC_ONE)) (portRef CE (instanceRef N_sout_1__REG)) (portRef CE (instanceRef N_sout_2__REG)) (portRef CE (instanceRef N_sout_3__REG)) (portRef CE (instanceRef N_sout_4__REG)) (portRef CE (instanceRef N_sout_5__REG)) (portRef CE (instanceRef N_sout_6__REG)) (portRef CE (instanceRef N_sout_7__REG)) ) ) (net GND (joined (portRef OUT (instanceRef GND_ZERO)) (portRef IN0 (instanceRef N_sout_0__D1_11)) (portRef IN1 (instanceRef N_sout_0__D1_11)) (portRef IN0 (instanceRef N_sout_1__D1_20)) (portRef IN1 (instanceRef N_sout_1__D1_20)) (portRef IN0 (instanceRef N_sout_2__D1_29)) (portRef IN1 (instanceRef N_sout_2__D1_29)) (portRef IN0 (instanceRef N_sout_3__D1_37)) (portRef IN1 (instanceRef N_sout_3__D1_37)) (portRef IN0 (instanceRef N_sout_4__D1_45)) (portRef IN1 (instanceRef N_sout_4__D1_45)) (portRef IN0 (instanceRef N_sout_5__D1_53)) (portRef IN1 (instanceRef N_sout_5__D1_53)) (portRef IN0 (instanceRef N_sout_6__D1_61)) (portRef IN1 (instanceRef N_sout_6__D1_61)) (portRef IN0 (instanceRef N_sout_7__D1_69)) (portRef IN1 (instanceRef N_sout_7__D1_69)) (portRef SET (instanceRef N_sout_0__REG)) (portRef SET (instanceRef N_sout_1__REG)) (portRef SET (instanceRef N_sout_2__REG)) (portRef SET (instanceRef N_sout_3__REG)) (portRef SET (instanceRef N_sout_4__REG)) (portRef SET (instanceRef N_sout_5__REG)) (portRef SET (instanceRef N_sout_6__REG)) (portRef SET (instanceRef N_sout_7__REG)) ) ) (net PRLD (joined (portRef RST (instanceRef N_sout_0__REG)) (portRef RST (instanceRef N_sout_1__REG)) (portRef RST (instanceRef N_sout_2__REG)) (portRef RST (instanceRef N_sout_3__REG)) (portRef RST (instanceRef N_sout_4__REG)) (portRef RST (instanceRef N_sout_5__REG)) (portRef RST (instanceRef N_sout_6__REG)) (portRef RST (instanceRef N_sout_7__REG)) ) (property INIT (string "0") (owner "Xilinx")) ) ) ) ) ) (design ex5 (cellRef ex5 (libraryRef ex5_lib) ) ))
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