time_sim.edn
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 1,355 行 · 第 1/4 页
EDN
1,355 行
(portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance (rename N_sout_7___66 "N_sout_7_&_66") (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) ) (instance N_sout_7__REG (viewRef view_1 (cellRef x_ff (libraryRef SIMPRIMS))) (property SUINHICLK (integer 1500) (unit TIME) (owner "Xilinx")) (property SUINLOCLK (integer 1500) (unit TIME) (owner "Xilinx")) (property HOLDINHICLK (integer 3000) (unit TIME) (owner "Xilinx")) (property HOLDINLOCLK (integer 3000) (unit TIME) (owner "Xilinx")) (property PWCLKHI (integer 5000) (unit TIME) (owner "Xilinx")) (property PWCLKLO (integer 5000) (unit TIME) (owner "Xilinx")) (portInstance OUT (property RISE (integer 500) (unit TIME) (owner "Xilinx")) (property FALL (integer 500) (unit TIME) (owner "Xilinx")) ) ) (instance N_sout_7__CLKF_PT_0_67 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 3000) (unit TIME) (owner "Xilinx")) (property FALL (integer 3000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 3000) (unit TIME) (owner "Xilinx")) (property FALL (integer 3000) (unit TIME) (owner "Xilinx")) ) ) (instance N_sout_7__CLKF_68 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_sout_7__D1_69 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_sout_7__D2_PT_0_70 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 6000) (unit TIME) (owner "Xilinx")) (property FALL (integer 6000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 6000) (unit TIME) (owner "Xilinx")) (property FALL (integer 6000) (unit TIME) (owner "Xilinx")) ) ) (instance N_sout_7__D2_71 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_sout_7__XOR (viewRef view_1 (cellRef x_xor2 (libraryRef SIMPRIMS))) ) (net sin (joined (portRef sin) (portRef PAD (instanceRef sin_PAD)) (portRef IN (instanceRef N_sin_14)) ) ) (net clk (joined (portRef clk) (portRef PAD (instanceRef clk_PAD)) (portRef IN (instanceRef N_clk_15)) ) ) (net (rename NlwRenamedSig_OI_sout_0__ "sout<0>") (joined (portRef sout_0__) (portRef PAD (instanceRef sout_0__PAD)) (portRef OUT (instanceRef sout_0___7)) (portRef IN (instanceRef sout_0__PIN_BUF__24)) ) ) (net (rename sout_1__ "sout<1>") (joined (portRef sout_1__) (portRef PAD (instanceRef sout_1__PAD)) (portRef OUT (instanceRef sout_1___16)) ) ) (net (rename sout_2__ "sout<2>") (joined (portRef sout_2__) (portRef PAD (instanceRef sout_2__PAD)) (portRef OUT (instanceRef sout_2___25)) ) ) (net (rename sout_3__ "sout<3>") (joined (portRef sout_3__) (portRef PAD (instanceRef sout_3__PAD)) (portRef OUT (instanceRef sout_3___33)) ) ) (net (rename sout_4__ "sout<4>") (joined (portRef sout_4__) (portRef PAD (instanceRef sout_4__PAD)) (portRef OUT (instanceRef sout_4___41)) ) ) (net (rename sout_5__ "sout<5>") (joined (portRef sout_5__) (portRef PAD (instanceRef sout_5__PAD)) (portRef OUT (instanceRef sout_5___49)) ) ) (net (rename sout_6__ "sout<6>") (joined (portRef sout_6__) (portRef PAD (instanceRef sout_6__PAD)) (portRef OUT (instanceRef sout_6___57)) ) ) (net (rename sout_7__ "sout<7>") (joined (portRef sout_7__) (portRef PAD (instanceRef sout_7__PAD)) (portRef OUT (instanceRef sout_7___65)) ) ) (net N_sout_0__Q (joined (portRef IN (instanceRef sout_0___7)) (portRef OUT (instanceRef N_sout_0__Q_8)) ) ) (net N_sout_0__Q_0 (joined (portRef IN (instanceRef N_sout_0__Q_8)) (portRef OUT (instanceRef N_sout_0__REG)) ) ) (net N_sout_0__D (joined (portRef IN (instanceRef N_sout_0__REG)) (portRef OUT (instanceRef N_sout_0__XOR)) ) ) (net N_sout_0__CLKF (joined (portRef CLK (instanceRef N_sout_0__REG)) (portRef OUT (instanceRef N_sout_0__CLKF_10)) ) ) (net N_clk (joined (portRef IN0 (instanceRef N_sout_0__CLKF_PT_0_9)) (portRef IN1 (instanceRef N_sout_0__CLKF_PT_0_9)) (portRef OUT (instanceRef N_clk_15)) (portRef IN0 (instanceRef N_sout_1__CLKF_PT_0_18)) (portRef IN1 (instanceRef N_sout_1__CLKF_PT_0_18)) (portRef IN0 (instanceRef N_sout_2__CLKF_PT_0_27)) (portRef IN1 (instanceRef N_sout_2__CLKF_PT_0_27)) (portRef IN0 (instanceRef N_sout_3__CLKF_PT_0_35)) (portRef IN1 (instanceRef N_sout_3__CLKF_PT_0_35)) (portRef IN0 (instanceRef N_sout_4__CLKF_PT_0_43)) (portRef IN1 (instanceRef N_sout_4__CLKF_PT_0_43)) (portRef IN0 (instanceRef N_sout_5__CLKF_PT_0_51)) (portRef IN1 (instanceRef N_sout_5__CLKF_PT_0_51)) (portRef IN0 (instanceRef N_sout_6__CLKF_PT_0_59)) (portRef IN1 (instanceRef N_sout_6__CLKF_PT_0_59)) (portRef IN0 (instanceRef N_sout_7__CLKF_PT_0_67)) (portRef IN1 (instanceRef N_sout_7__CLKF_PT_0_67)) ) ) (net N_sout_0__CLKF_PT_0 (joined (portRef OUT (instanceRef N_sout_0__CLKF_PT_0_9)) (portRef IN0 (instanceRef N_sout_0__CLKF_10)) (portRef IN1 (instanceRef N_sout_0__CLKF_10)) ) ) (net N_sout_0__D1 (joined (portRef OUT (instanceRef N_sout_0__D1_11)) (portRef IN0 (instanceRef N_sout_0__XOR)) ) ) (net N_sin (joined (portRef IN0 (instanceRef N_sout_0__D2_PT_0_12)) (portRef IN1 (instanceRef N_sout_0__D2_PT_0_12)) (portRef OUT (instanceRef N_sin_14)) ) ) (net N_sout_0__D2_PT_0 (joined (portRef OUT (instanceRef N_sout_0__D2_PT_0_12)) (portRef IN0 (instanceRef N_sout_0__D2_13)) (portRef IN1 (instanceRef N_sout_0__D2_13)) ) ) (net N_sout_0__D2 (joined (portRef OUT (instanceRef N_sout_0__D2_13)) (portRef IN1 (instanceRef N_sout_0__XOR)) ) ) (net N_sout_1__Q (joined (portRef IN (instanceRef sout_1___16)) (portRef OUT (instanceRef N_sout_1__Q_17)) ) ) (net N_sout_1__Q_1 (joined (portRef IN (instanceRef N_sout_1__Q_17)) (portRef OUT (instanceRef N_sout_1__REG)) (portRef IN (instanceRef N_sout_1__FBK_23)) ) ) (net N_sout_1__D (joined (portRef IN (instanceRef N_sout_1__REG)) (portRef OUT (instanceRef N_sout_1__XOR)) ) ) (net N_sout_1__CLKF (joined (portRef CLK (instanceRef N_sout_1__REG)) (portRef OUT (instanceRef N_sout_1__CLKF_19)) ) ) (net N_sout_1__CLKF_PT_0 (joined (portRef OUT (instanceRef N_sout_1__CLKF_PT_0_18)) (portRef IN0 (instanceRef N_sout_1__CLKF_19)) (portRef IN1 (instanceRef N_sout_1__CLKF_19)) ) ) (net N_sout_1__D1 (joined (portRef OUT (instanceRef N_sout_1__D1_20)) (portRef IN0 (instanceRef N_sout_1__XOR)) ) ) (net sout_0__PIN_BUF_ (joined (portRef IN0 (instanceRef N_sout_1__D2_PT_0_21)) (portRef IN1 (instanceRef N_sout_1__D2_PT_0_21)) (portRef OUT (instanceRef sout_0__PIN_BUF__24)) ) ) (net N_sout_1__D2_PT_0 (joined (portRef OUT (instanceRef N_sout_1__D2_PT_0_21)) (portRef IN0 (instanceRef N_sout_1__D2_22)) (portRef IN1 (instanceRef N_sout_1__D2_22)) ) ) (net N_sout_1__D2 (joined (portRef OUT (instanceRef N_sout_1__D2_22)) (portRef IN1 (instanceRef N_sout_1__XOR)) ) ) (net N_sout_1__FBK (joined (portRef OUT (instanceRef N_sout_1__FBK_23)) (portRef IN0 (instanceRef N_sout_2__D2_PT_0_30)) (portRef IN1 (instanceRef N_sout_2__D2_PT_0_30)) ) ) (net N_sout_2__Q (joined (portRef IN (instanceRef sout_2___25)) (portRef OUT (instanceRef N_sout_2__Q_26)) ) ) (net N_sout_2__Q_2 (joined (portRef IN (instanceRef N_sout_2__Q_26)) (portRef OUT (instanceRef N_sout_2__REG)) (portRef IN (instanceRef N_sout_2__FBK_32)) ) ) (net N_sout_2__D (joined (portRef IN (instanceRef N_sout_2__REG)) (portRef OUT (instanceRef N_sout_2__XOR)) ) ) (net N_sout_2__CLKF (joined (portRef CLK (instanceRef N_sout_2__REG)) (portRef OUT (instanceRef N_sout_2__CLKF_28)) ) ) (net N_sout_2__CLKF_PT_0 (joined (portRef OUT (instanceRef N_sout_2__CLKF_PT_0_27)) (portRef IN0 (instanceRef N_sout_2__CLKF_28)) (portRef IN1 (instanceRef N_sout_2__CLKF_28)) ) ) (net N_sout_2__D1 (joined (portRef OUT (instanceRef N_sout_2__D1_29)) (portRef IN0 (instanceRef N_sout_2__XOR)) ) ) (net N_sout_2__D2_PT_0 (joined (portRef OUT (instanceRef N_sout_2__D2_PT_0_30)) (portRef IN0 (instanceRef N_sout_2__D2_31)) (portRef IN1 (instanceRef N_sout_2__D2_31)) ) ) (net N_sout_2__D2 (joined (portRef OUT (instanceRef N_sout_2__D2_31)) (portRef IN1 (instanceRef N_sout_2__XOR)) ) ) (net N_sout_2__FBK (joined (portRef OUT (instanceRef N_sout_2__FBK_32)) (portRef IN0 (instanceRef N_sout_3__D2_PT_0_38)) (portRef IN1 (instanceRef N_sout_3__D2_PT_0_38)) ) ) (net N_sout_3__Q (joined (portRef IN (instanceRef sout_3___33)) (portRef OUT (instanceRef N_sout_3__Q_34)) ) ) (net N_sout_3__Q_3 (joined (portRef IN (instanceRef N_sout_3__Q_34)) (portRef OUT (instanceRef N_sout_3__REG)) (portRef IN (instanceRef N_sout_3__FBK_40)) )
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