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📁 [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][
💻 VM6
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NDS Database:  version E.38

NDS_INFO | xc9500 | 957284 | XC9572-7-PC84

DEVICE | 9572 | 957284 | 

NETWORK | ex5 | 0 | 0 | 209731591

INPUT_INSTANCE | 0 | 0 | NULL | N_sin | EX5_COPY_0_COPY_0 | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 5 | II_IN
NODE | sin | 265 | PI | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
NODE | N_sin | 240 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_sin | 0 | 5 | II_IMUX

INPUT_INSTANCE | 0 | 0 | NULL | N_clk | EX5_COPY_0_COPY_0 | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 5 | II_IN
NODE | clk | 266 | PI | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
NODE | N_clk | 241 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX

MACROCELL_INSTANCE | PrldLow+OptxMapped+OeInv | N_sout<0> | EX5_COPY_0_COPY_0 | 2290091008 | 2 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_sin | 240 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_sin | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 241 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | N_sout<0>$Q | 242 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<0>.Q | N_sout<0> | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | N_sout<0> | 243 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<0>.Q | N_sout<0> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | N_sout<0>.SI | N_sout<0> | 0 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_sin | 240 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_sin | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 241 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | N_sout<0>.D1 | 268 | ? | 0 | 4096 | N_sout<0> | NULL | NULL | N_sout<0>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | N_sout<0>.D2 | 269 | ? | 0 | 4096 | N_sout<0> | NULL | NULL | N_sout<0>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | N_sin
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | N_sout<0>.CLKF | 270 | ? | 0 | 4096 | N_sout<0> | NULL | NULL | N_sout<0>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk

SRFF_INSTANCE | N_sout<0>.REG | N_sout<0> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | N_sout<0>.D | 267 | ? | 0 | 0 | N_sout<0> | NULL | NULL | N_sout<0>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | N_sout<0>.CLKF | 270 | ? | 0 | 4096 | N_sout<0> | NULL | NULL | N_sout<0>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | N_sout<0>.Q | 271 | ? | 0 | 0 | N_sout<0> | NULL | NULL | N_sout<0>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+OptxMapped+ClkInv | N_sout<1> | EX5_COPY_0_COPY_0 | 2222982144 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 241 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | sout<0>_PIN_BUF_ | 313 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | Pfbk_Created_sout<0> | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | N_sout<1>$Q | 244 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<1>.Q | N_sout<1> | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | N_sout<1> | 245 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<1>.Q | N_sout<1> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | N_sout<1>.FBK | 307 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<1>.Q | N_sout<1> | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | N_sout<1>.SI | N_sout<1> | 0 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 241 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | sout<0>_PIN_BUF_ | 313 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | Pfbk_Created_sout<0> | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | N_sout<1>.D1 | 273 | ? | 0 | 4096 | N_sout<1> | NULL | NULL | N_sout<1>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | N_sout<1>.D2 | 274 | ? | 0 | 4096 | N_sout<1> | NULL | NULL | N_sout<1>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | sout<0>_PIN_BUF_
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | N_sout<1>.CLKF | 275 | ? | 0 | 4096 | N_sout<1> | NULL | NULL | N_sout<1>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk

SRFF_INSTANCE | N_sout<1>.REG | N_sout<1> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | N_sout<1>.D | 272 | ? | 0 | 0 | N_sout<1> | NULL | NULL | N_sout<1>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | N_sout<1>.CLKF | 275 | ? | 0 | 4096 | N_sout<1> | NULL | NULL | N_sout<1>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | N_sout<1>.Q | 276 | ? | 0 | 0 | N_sout<1> | NULL | NULL | N_sout<1>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+OptxMapped+ClkInv | N_sout<2> | EX5_COPY_0_COPY_0 | 2222982144 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 241 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_sout<1>.FBK | 307 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<1>.Q | N_sout<1> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | N_sout<2>$Q | 246 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<2>.Q | N_sout<2> | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | N_sout<2> | 247 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<2>.Q | N_sout<2> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | N_sout<2>.FBK | 308 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<2>.Q | N_sout<2> | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | N_sout<2>.SI | N_sout<2> | 0 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 241 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_sout<1>.FBK | 307 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<1>.Q | N_sout<1> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | N_sout<2>.D1 | 278 | ? | 0 | 4096 | N_sout<2> | NULL | NULL | N_sout<2>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | N_sout<2>.D2 | 279 | ? | 0 | 4096 | N_sout<2> | NULL | NULL | N_sout<2>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | N_sout<1>.FBK
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | N_sout<2>.CLKF | 280 | ? | 0 | 4096 | N_sout<2> | NULL | NULL | N_sout<2>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk

SRFF_INSTANCE | N_sout<2>.REG | N_sout<2> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | N_sout<2>.D | 277 | ? | 0 | 0 | N_sout<2> | NULL | NULL | N_sout<2>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | N_sout<2>.CLKF | 280 | ? | 0 | 4096 | N_sout<2> | NULL | NULL | N_sout<2>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | N_sout<2>.Q | 281 | ? | 0 | 0 | N_sout<2> | NULL | NULL | N_sout<2>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+OptxMapped+ClkInv | N_sout<3> | EX5_COPY_0_COPY_0 | 2222982144 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 241 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_sout<2>.FBK | 308 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<2>.Q | N_sout<2> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | N_sout<3>$Q | 248 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<3>.Q | N_sout<3> | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | N_sout<3> | 249 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<3>.Q | N_sout<3> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | N_sout<3>.FBK | 309 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<3>.Q | N_sout<3> | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | N_sout<3>.SI | N_sout<3> | 0 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 241 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_sout<2>.FBK | 308 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<2>.Q | N_sout<2> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | N_sout<3>.D1 | 283 | ? | 0 | 4096 | N_sout<3> | NULL | NULL | N_sout<3>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | N_sout<3>.D2 | 284 | ? | 0 | 4096 | N_sout<3> | NULL | NULL | N_sout<3>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | N_sout<2>.FBK
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | N_sout<3>.CLKF | 285 | ? | 0 | 4096 | N_sout<3> | NULL | NULL | N_sout<3>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk

SRFF_INSTANCE | N_sout<3>.REG | N_sout<3> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | N_sout<3>.D | 282 | ? | 0 | 0 | N_sout<3> | NULL | NULL | N_sout<3>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | N_sout<3>.CLKF | 285 | ? | 0 | 4096 | N_sout<3> | NULL | NULL | N_sout<3>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | N_sout<3>.Q | 286 | ? | 0 | 0 | N_sout<3> | NULL | NULL | N_sout<3>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+OptxMapped+ClkInv | N_sout<4> | EX5_COPY_0_COPY_0 | 2222982144 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 241 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_sout<3>.FBK | 309 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<3>.Q | N_sout<3> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | N_sout<4>$Q | 250 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<4>.Q | N_sout<4> | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | N_sout<4> | 251 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<4>.Q | N_sout<4> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | N_sout<4>.FBK | 310 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<4>.Q | N_sout<4> | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | N_sout<4>.SI | N_sout<4> | 0 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_clk | 241 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | NULL | N_clk | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_sout<3>.FBK | 309 | ? | 0 | 0 | EX5_COPY_0_COPY_0 | NULL | N_sout<3>.Q | N_sout<3> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | N_sout<4>.D1 | 288 | ? | 0 | 4096 | N_sout<4> | NULL | NULL | N_sout<4>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | N_sout<4>.D2 | 289 | ? | 0 | 4096 | N_sout<4> | NULL | NULL | N_sout<4>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | N_sout<3>.FBK
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | N_sout<4>.CLKF | 290 | ? | 0 | 4096 | N_sout<4> | NULL | NULL | N_sout<4>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk

SRFF_INSTANCE | N_sout<4>.REG | N_sout<4> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | N_sout<4>.D | 287 | ? | 0 | 0 | N_sout<4> | NULL | NULL | N_sout<4>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | N_sout<4>.CLKF | 290 | ? | 0 | 4096 | N_sout<4> | NULL | NULL | N_sout<4>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | N_clk
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