ex5.data

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

MODELDATA
MODELDATA_VERSION "v1998.8"
DESIGN "ex5";

/* port drive, load, max capacitance and max transition in data file */
PORTDATA
sin: MAXTRANS(0.0);
clk: MAXTRANS(0.0);
sout<0>: MAXTRANS(0.0);
sout<1>: MAXTRANS(0.0);
sout<2>: MAXTRANS(0.0);
sout<3>: MAXTRANS(0.0);
sout<4>: MAXTRANS(0.0);
sout<5>: MAXTRANS(0.0);
sout<6>: MAXTRANS(0.0);
sout<7>: MAXTRANS(0.0);
ENDPORTDATA

/* timing arc data */
TIMINGDATA

ARCDATA
clk_sout<0>_delay:
CELL_RISE(scalar) {
  VALUES("8.5");
}
CELL_FALL(scalar) {
  VALUES("8.5");
}
ENDARCDATA

ARCDATA
clk_sout<1>_delay:
CELL_RISE(scalar) {
  VALUES("8.5");
}
CELL_FALL(scalar) {
  VALUES("8.5");
}
ENDARCDATA

ARCDATA
clk_sout<2>_delay:
CELL_RISE(scalar) {
  VALUES("8.5");
}
CELL_FALL(scalar) {
  VALUES("8.5");
}
ENDARCDATA

ARCDATA
clk_sout<3>_delay:
CELL_RISE(scalar) {
  VALUES("8.5");
}
CELL_FALL(scalar) {
  VALUES("8.5");
}
ENDARCDATA

ARCDATA
clk_sout<4>_delay:
CELL_RISE(scalar) {
  VALUES("8.5");
}
CELL_FALL(scalar) {
  VALUES("8.5");
}
ENDARCDATA

ARCDATA
clk_sout<5>_delay:
CELL_RISE(scalar) {
  VALUES("8.5");
}
CELL_FALL(scalar) {
  VALUES("8.5");
}
ENDARCDATA

ARCDATA
clk_sout<6>_delay:
CELL_RISE(scalar) {
  VALUES("8.5");
}
CELL_FALL(scalar) {
  VALUES("8.5");
}
ENDARCDATA

ARCDATA
clk_sout<7>_delay:
CELL_RISE(scalar) {
  VALUES("8.5");
}
CELL_FALL(scalar) {
  VALUES("8.5");
}
ENDARCDATA

ARCDATA
sin_clk_setup:
CONSTRAINT(scalar) {
  VALUES("2");
}
ENDARCDATA

ARCDATA
sin_clk_hold:
CONSTRAINT(scalar) {
  VALUES("2.5");
}
ENDARCDATA

ENDTIMINGDATA
ENDMODELDATA