📄 ex5.rpt
字号:
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 25 I/O
(unused) 0 0 0 5 FB3_2 17 I/O
(unused) 0 0 0 5 FB3_3 31 I/O
(unused) 0 0 0 5 FB3_4 32 I/O
(unused) 0 0 0 5 FB3_5 19 I/O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 35 I/O
(unused) 0 0 0 5 FB3_8 21 I/O
(unused) 0 0 0 5 FB3_9 26 I/O
(unused) 0 0 0 5 FB3_10 40 I/O
(unused) 0 0 0 5 FB3_11 33 I/O
(unused) 0 0 0 5 FB3_12 41 I/O
(unused) 0 0 0 5 FB3_13 43 I/O
(unused) 0 0 0 5 FB3_14 36 I/O
(unused) 0 0 0 5 FB3_15 37 I/O
(unused) 0 0 0 5 FB3_16 45 I/O
(unused) 0 0 0 5 FB3_17 39 I/O
(unused) 0 0 0 5 FB3_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 2/34
Number of signals used by logic mapping into function block: 2
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 46 I/O
(unused) 0 0 0 5 FB4_2 44 I/O
(unused) 0 0 0 5 FB4_3 51 I/O
(unused) 0 0 0 5 FB4_4 52 I/O
(unused) 0 0 0 5 FB4_5 47 I/O
(unused) 0 0 0 5 FB4_6 54 I/O
(unused) 0 0 0 5 FB4_7 55 I/O
(unused) 0 0 0 5 FB4_8 48 I/O
(unused) 0 0 0 5 FB4_9 50 I/O
(unused) 0 0 0 5 FB4_10 57 I/O
(unused) 0 0 0 5 FB4_11 53 I/O
(unused) 0 0 0 5 FB4_12 58 I/O
(unused) 0 0 0 5 FB4_13 61 I/O
(unused) 0 0 0 5 FB4_14 56 I/O
(unused) 0 0 0 5 FB4_15 65 I/O
(unused) 0 0 0 5 FB4_16 62 I/O
sout<0> 2 0 0 3 FB4_17 STD 66 I/O I/O
(unused) 0 0 0 5 FB4_18 (b)
Signals Used by Logic in Function Block
1: clk 2: sin
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
sout<0> XX...................................... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"sout<0>" := sin
"sout<0>".CLKF = clk
"sout<0>".PRLD = GND
"sout<1>" := "sout<0>".PIN
"sout<1>".CLKF = clk
"sout<1>".PRLD = GND
"sout<2>" := "N_sout<1>.FBK".LFBK
"sout<2>".CLKF = clk
"sout<2>".PRLD = GND
"sout<3>" := "N_sout<2>.FBK".LFBK
"sout<3>".CLKF = clk
"sout<3>".PRLD = GND
"sout<4>" := "N_sout<3>.FBK".LFBK
"sout<4>".CLKF = clk
"sout<4>".PRLD = GND
"sout<5>" := "N_sout<4>.FBK".LFBK
"sout<5>".CLKF = clk
"sout<5>".PRLD = GND
"sout<6>" := "N_sout<5>.FBK".LFBK
"sout<6>".CLKF = clk
"sout<6>".PRLD = GND
"sout<7>" := "N_sout<6>.FBK".LFBK
"sout<7>".CLKF = clk
"sout<7>".PRLD = GND
**************************** Device Pin Out ****************************
Device : XC9572-7-PC84
s s
o o
u u
t t
T T T G T T T T T T T T T T T T T V < < T
I I I N I I I I I I I I I I I I I C 7 6 I
E E E D E E E E E E E E E E E E E C > > E
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
TIE | 12 74 | TIE
TIE | 13 73 | VCC
TIE | 14 72 | sout<5>
TIE | 15 71 | sout<3>
GND | 16 70 | sout<4>
TIE | 17 69 | sout<1>
TIE | 18 68 | sout<2>
TIE | 19 67 | TIE
sin | 20 66 | sout<0>
TIE | 21 XC9572-7-PC84 65 | TIE
VCC | 22 64 | VCC
clk | 23 63 | TIE
TIE | 24 62 | TIE
TIE | 25 61 | TIE
TIE | 26 60 | GND
GND | 27 59 | TDO
TDI | 28 58 | TIE
TMS | 29 57 | TIE
TCK | 30 56 | TIE
TIE | 31 55 | TIE
TIE | 32 54 | TIE
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
T T T T T V T T T G T T T T T T G T T T T
I I I I I C I I I N I I I I I I N I I I I
E E E E E C E E E D E E E E E E D E E E E
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC95*-*-*
Use Timing Constraints : ON
Use Design Location Constraints : ON
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : ON
Collapsing pterm limit : 25
Collapsing input limit : 36
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