ex5.rpt

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cpldfit:  version E.38                              Xilinx Inc.
                                  Fitter Report
Design Name: ex5                                 Date:  3-11-2008, 11:18PM
Device Used: XC9572-7-PC84
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
8  /72  ( 11%) 16  /360  (  4%) 8  /72  ( 11%) 10 /69  ( 14%) 10 /144 (  6%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    2           2    |  I/O              :     8       55
Output        :    7           7    |  GCK/IO           :     0        3
Bidirectional :    1           1    |  GTS/IO           :     2        0
GCK           :    0           0    |  GSR/IO           :     0        1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     10          10

MACROCELL RESOURCES:

Total Macrocells Available                    72
Registered Macrocells                          8
Non-registered Macrocell driving I/O           0

GLOBAL RESOURCES:

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 8 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 8 macrocells used (MC).

End of Resource Summary
****************************  Errors and Warnings  *************************

ERROR:Cpld:828 - 'sout<0>' is assigned to an invalid location ('P66') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<0>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<1>' is assigned to an invalid location ('P69') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<1>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<2>' is assigned to an invalid location ('P68') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<2>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<3>' is assigned to an invalid location ('P71') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<3>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<4>' is assigned to an invalid location ('P70') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<4>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<5>' is assigned to an invalid location ('P72') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<5>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<6>' is assigned to an invalid location ('P76') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<6>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<7>' is assigned to an invalid location ('P77') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<7>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'clk' is assigned to an invalid location ('P23') for this
   device.  This will prevent the design from fitting on the current device.
   'clk' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<0>' is assigned to an invalid location ('P66') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<0>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<1>' is assigned to an invalid location ('P69') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<1>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<2>' is assigned to an invalid location ('P68') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<2>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<3>' is assigned to an invalid location ('P71') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<3>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<4>' is assigned to an invalid location ('P70') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<4>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<5>' is assigned to an invalid location ('P72') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<5>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<6>' is assigned to an invalid location ('P76') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<6>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sout<7>' is assigned to an invalid location ('P77') for this
   device.  This will prevent the design from fitting on the current device.
   'sout<7>' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'clk' is assigned to an invalid location ('P23') for this
   device.  This will prevent the design from fitting on the current device.
   'clk' must be reassigned before attempting a re-fit.
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
sout<0>             2       2       FB4_17  STD  FAST 66   I/O       I/O
sout<1>             2       2       FB2_2   STD  FAST 69   I/O       O
sout<2>             2       2       FB2_4   STD  FAST 68   I/O       O
sout<3>             2       2       FB2_6   STD  FAST 71   I/O       O
sout<4>             2       2       FB2_5   STD  FAST 70   I/O       O
sout<5>             2       2       FB2_8   STD  FAST 72   I/O       O
sout<6>             2       2       FB2_7   STD  FAST 76   GTS/I/O   O
sout<7>             2       2       FB2_11  STD  FAST 77   GTS/I/O   O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
clk                                 FB1_16            23   I/O       I
sin                                 FB1_13            20   I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           0           0           0            0         0/0       18   
FB2           7           8           8           14         7/0       17   
FB3           0           0           0            0         0/0       17   
FB4           1           2           2            2         0/1       17   
            ----                                -----       -----     ----- 
              8                                   16         7/1       69   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB1_1         4     I/O     
(unused)              0       0     0   5     FB1_2         1     I/O     
(unused)              0       0     0   5     FB1_3         6     I/O     
(unused)              0       0     0   5     FB1_4         7     I/O     
(unused)              0       0     0   5     FB1_5         2     I/O     
(unused)              0       0     0   5     FB1_6         3     I/O     
(unused)              0       0     0   5     FB1_7         11    I/O     
(unused)              0       0     0   5     FB1_8         5     I/O     
(unused)              0       0     0   5     FB1_9         9     GCK/I/O 
(unused)              0       0     0   5     FB1_10        13    I/O     
(unused)              0       0     0   5     FB1_11        10    GCK/I/O 
(unused)              0       0     0   5     FB1_12        18    I/O     
(unused)              0       0     0   5     FB1_13        20    I/O     I
(unused)              0       0     0   5     FB1_14        12    GCK/I/O 
(unused)              0       0     0   5     FB1_15        14    I/O     
(unused)              0       0     0   5     FB1_16        23    I/O     I
(unused)              0       0     0   5     FB1_17        15    I/O     
(unused)              0       0     0   5     FB1_18        24    I/O     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               8/28
Number of signals used by logic mapping into function block:  8
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB2_1         63    I/O     
sout<1>               2       0     0   3     FB2_2   STD   69    I/O     O
(unused)              0       0     0   5     FB2_3         67    I/O     
sout<2>               2       0     0   3     FB2_4   STD   68    I/O     O
sout<4>               2       0     0   3     FB2_5   STD   70    I/O     O
sout<3>               2       0     0   3     FB2_6   STD   71    I/O     O
sout<6>               2       0     0   3     FB2_7   STD   76    GTS/I/O O
sout<5>               2       0     0   3     FB2_8   STD   72    I/O     O
(unused)              0       0     0   5     FB2_9         74    GSR/I/O 
(unused)              0       0     0   5     FB2_10        75    I/O     
sout<7>               2       0     0   3     FB2_11  STD   77    GTS/I/O O
(unused)              0       0     0   5     FB2_12        79    I/O     
(unused)              0       0     0   5     FB2_13        80    I/O     
(unused)              0       0     0   5     FB2_14        81    I/O     
(unused)              0       0     0   5     FB2_15        83    I/O     
(unused)              0       0     0   5     FB2_16        82    I/O     
(unused)              0       0     0   5     FB2_17        84    I/O     
(unused)              0       0     0   5     FB2_18              (b)     

Signals Used by Logic in Function Block
  1: clk                4: "N_sout<3>.FBK".LFBK 
                                              7: "N_sout<6>.FBK".LFBK 
  2: "N_sout<1>.FBK".LFBK 
                        5: "N_sout<4>.FBK".LFBK 
                                              8: "sout<0>".PIN 
  3: "N_sout<2>.FBK".LFBK 
                        6: "N_sout<5>.FBK".LFBK 
                                            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
sout<1>              X......X................................ 2       2
sout<2>              XX...................................... 2       2
sout<4>              X..X.................................... 2       2
sout<3>              X.X..................................... 2       2
sout<6>              X....X.................................. 2       2
sout<5>              X...X................................... 2       2
sout<7>              X.....X................................. 2       2
                    0----+----1----+----2----+----3----+----4