ex5.gyd

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

Pin Freeze File:  version E.38

957284 XC9572-7-PC84
clk S:PIN23
sin S:PIN20
sout<0> S:PIN66
sout<1> S:PIN69
sout<2> S:PIN68
sout<3> S:PIN71
sout<4> S:PIN70
sout<5> S:PIN72
sout<6> S:PIN76
sout<7> S:PIN77


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.


PARTITION FB2_2 "N_sout<1>"
PARTITION FB2_4 "N_sout<2>" "N_sout<4>" "N_sout<3>" "N_sout<6>"
		 "N_sout<5>"
PARTITION FB2_11 "N_sout<7>"


PARTITION FB4_17 "N_sout<0>"