ex1.mod

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MOD 代码 · 共 23 行

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex1";

/* port names and type */
INPUT S:PIN23 = b;
INPUT S:PIN20 = a;
INPUT S:PIN24 = c_in;
OUTPUT S:PIN52 = c_out;
OUTPUT S:PIN56 = sum;

/* timing arc definitions */
b_c_out_delay: DELAY b c_out;
a_c_out_delay: DELAY a c_out;
c_in_c_out_delay: DELAY c_in c_out;
b_sum_delay: DELAY b sum;
a_sum_delay: DELAY a sum;
c_in_sum_delay: DELAY c_in sum;

/* timing check arc definitions */

ENDMODEL