ex1.data

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

MODELDATA
MODELDATA_VERSION "v1998.8"
DESIGN "ex1";

/* port drive, load, max capacitance and max transition in data file */
PORTDATA
b: MAXTRANS(0.0);
a: MAXTRANS(0.0);
c_in: MAXTRANS(0.0);
c_out: MAXTRANS(0.0);
sum: MAXTRANS(0.0);
ENDPORTDATA

/* timing arc data */
TIMINGDATA

ARCDATA
b_c_out_delay:
CELL_RISE(scalar) {
  VALUES("7.5");
}
CELL_FALL(scalar) {
  VALUES("7.5");
}
ENDARCDATA

ARCDATA
a_c_out_delay:
CELL_RISE(scalar) {
  VALUES("7.5");
}
CELL_FALL(scalar) {
  VALUES("7.5");
}
ENDARCDATA

ARCDATA
c_in_c_out_delay:
CELL_RISE(scalar) {
  VALUES("7.5");
}
CELL_FALL(scalar) {
  VALUES("7.5");
}
ENDARCDATA

ARCDATA
b_sum_delay:
CELL_RISE(scalar) {
  VALUES("7.5");
}
CELL_FALL(scalar) {
  VALUES("7.5");
}
ENDARCDATA

ARCDATA
a_sum_delay:
CELL_RISE(scalar) {
  VALUES("7.5");
}
CELL_FALL(scalar) {
  VALUES("7.5");
}
ENDARCDATA

ARCDATA
c_in_sum_delay:
CELL_RISE(scalar) {
  VALUES("7.5");
}
CELL_FALL(scalar) {
  VALUES("7.5");
}
ENDARCDATA

ENDTIMINGDATA
ENDMODELDATA