ex1.gyd

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

Pin Freeze File:  version E.38

9510884 XC95108-7-PC84
a S:PIN20
b S:PIN23
c_in S:PIN24
c_out S:PIN52
sum S:PIN56


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.






PARTITION FB6_11 N_c_out
PARTITION FB6_17 N_sum