time_sim.edn

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

                (property FALL (integer 2500) (unit TIME) (owner "Xilinx"))
              )
            )
            (instance sum_PAD
              (viewRef view_1 (cellRef x_opad (libraryRef SIMPRIMS)))
            )
            (instance sum_10
              (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS)))
              (portInstance OUT
                (property RISE (integer 2500) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 2500) (unit TIME) (owner "Xilinx"))
              )
            )
            (instance N_sum_11
              (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS)))
            )
            (instance N_sum_REG
              (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS)))
              (portInstance OUT
                (property RISE (integer 500) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 500) (unit TIME) (owner "Xilinx"))
              )
            )
            (instance N_sum_D1_PT_0_12
              (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS)))
              (portInstance IN0
                (property RISE (integer 2000) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 2000) (unit TIME) (owner "Xilinx"))
              )
              (portInstance IN1
                (property RISE (integer 2000) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 2000) (unit TIME) (owner "Xilinx"))
              )
            )
            (instance N_sum_D1_13
              (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS)))
            )
            (instance N_sum_D2_PT_0_14
              (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS)))
              (portInstance IN0
                (property RISE (integer 2000) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 2000) (unit TIME) (owner "Xilinx"))
              )
              (portInstance IN1
                (property RISE (integer 2000) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 2000) (unit TIME) (owner "Xilinx"))
              )
            )
            (instance N_sum_D2_PT_1_15
              (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS)))
              (portInstance IN0
                (property RISE (integer 2000) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 2000) (unit TIME) (owner "Xilinx"))
              )
              (portInstance IN1
                (property RISE (integer 2000) (unit TIME) (owner "Xilinx"))
                (property FALL (integer 2000) (unit TIME) (owner "Xilinx"))
              )
            )
            (instance N_sum_D2_16
              (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS)))
            )
            (instance N_sum_XOR
              (viewRef view_1 (cellRef x_xor2 (libraryRef SIMPRIMS)))
            )
            (instance NlwInverterBlock_N_sum_D2_PT_1_IN0
              (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS)))
            )
            (instance NlwInverterBlock_N_sum_D2_PT_1_IN1
              (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS)))
            )
            (instance NlwInverterBlock_N_sum_XOR_IN0
              (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS)))
            )
            (net b
              (joined
                (portRef b)
                (portRef PAD (instanceRef b_PAD))
                (portRef IN (instanceRef N_b_7))
              )
            )
            (net a
              (joined
                (portRef a)
                (portRef PAD (instanceRef a_PAD))
                (portRef IN (instanceRef N_a_8))
              )
            )
            (net c_in
              (joined
                (portRef c_in)
                (portRef PAD (instanceRef c_in_PAD))
                (portRef IN (instanceRef N_c_in_9))
              )
            )
            (net c_out
              (joined
                (portRef c_out)
                (portRef PAD (instanceRef c_out_PAD))
                (portRef OUT (instanceRef c_out_0))
              )
            )
            (net sum
              (joined
                (portRef sum)
                (portRef PAD (instanceRef sum_PAD))
                (portRef OUT (instanceRef sum_10))
              )
            )
            (net N_c_out
              (joined
                (portRef IN (instanceRef c_out_0))
                (portRef OUT (instanceRef N_c_out_1))
              )
            )
            (net N_c_out_Q
              (joined
                (portRef IN (instanceRef N_c_out_1))
                (portRef OUT (instanceRef N_c_out_REG))
              )
            )
            (net N_c_out_D
              (joined
                (portRef IN (instanceRef N_c_out_REG))
                (portRef OUT (instanceRef N_c_out_XOR))
              )
            )
            (net N_c_out_D1
              (joined
                (portRef OUT (instanceRef N_c_out_D1_2))
                (portRef IN0 (instanceRef N_c_out_XOR))
              )
            )
            (net N_b
              (joined
                (portRef IN0 (instanceRef N_c_out_D2_PT_0_3))
                (portRef IN0 (instanceRef N_c_out_D2_PT_1_4))
                (portRef OUT (instanceRef N_b_7))
                (portRef IN0 (instanceRef N_sum_D2_PT_0_14))
                (portRef IN (instanceRef NlwInverterBlock_N_sum_D2_PT_1_IN0))
              )
            )
            (net N_a
              (joined
                (portRef IN1 (instanceRef N_c_out_D2_PT_0_3))
                (portRef IN0 (instanceRef N_c_out_D2_PT_2_5))
                (portRef OUT (instanceRef N_a_8))
                (portRef IN0 (instanceRef N_sum_D1_PT_0_12))
                (portRef IN1 (instanceRef N_sum_D1_PT_0_12))
              )
            )
            (net N_c_out_D2_PT_0
              (joined
                (portRef OUT (instanceRef N_c_out_D2_PT_0_3))
                (portRef IN0 (instanceRef N_c_out_D2_6))
              )
            )
            (net N_c_in
              (joined
                (portRef IN1 (instanceRef N_c_out_D2_PT_1_4))
                (portRef IN1 (instanceRef N_c_out_D2_PT_2_5))
                (portRef OUT (instanceRef N_c_in_9))
                (portRef IN1 (instanceRef N_sum_D2_PT_0_14))
                (portRef IN (instanceRef NlwInverterBlock_N_sum_D2_PT_1_IN1))
              )
            )
            (net N_c_out_D2_PT_1
              (joined
                (portRef OUT (instanceRef N_c_out_D2_PT_1_4))
                (portRef IN1 (instanceRef N_c_out_D2_6))
              )
            )
            (net N_c_out_D2_PT_2
              (joined
                (portRef OUT (instanceRef N_c_out_D2_PT_2_5))
                (portRef IN2 (instanceRef N_c_out_D2_6))
              )
            )
            (net N_c_out_D2
              (joined
                (portRef OUT (instanceRef N_c_out_D2_6))
                (portRef IN1 (instanceRef N_c_out_XOR))
              )
            )
            (net N_sum
              (joined
                (portRef IN (instanceRef sum_10))
                (portRef OUT (instanceRef N_sum_11))
              )
            )
            (net N_sum_Q
              (joined
                (portRef IN (instanceRef N_sum_11))
                (portRef OUT (instanceRef N_sum_REG))
              )
            )
            (net N_sum_D
              (joined
                (portRef IN (instanceRef N_sum_REG))
                (portRef OUT (instanceRef N_sum_XOR))
              )
            )
            (net N_sum_D1_PT_0
              (joined
                (portRef OUT (instanceRef N_sum_D1_PT_0_12))
                (portRef IN0 (instanceRef N_sum_D1_13))
                (portRef IN1 (instanceRef N_sum_D1_13))
              )
            )
            (net N_sum_D1
              (joined
                (portRef OUT (instanceRef N_sum_D1_13))
                (portRef IN (instanceRef NlwInverterBlock_N_sum_XOR_IN0))
              )
            )
            (net N_sum_D2_PT_0
              (joined
                (portRef OUT (instanceRef N_sum_D2_PT_0_14))
                (portRef IN0 (instanceRef N_sum_D2_16))
              )
            )
            (net N_sum_D2_PT_1
              (joined
                (portRef OUT (instanceRef N_sum_D2_PT_1_15))
                (portRef IN1 (instanceRef N_sum_D2_16))
              )
            )
            (net N_sum_D2
              (joined
                (portRef OUT (instanceRef N_sum_D2_16))
                (portRef IN1 (instanceRef N_sum_XOR))
              )
            )
            (net GND
              (joined
                (portRef OUT (instanceRef GND_ZERO))
                (portRef IN0 (instanceRef N_c_out_D1_2))
                (portRef IN1 (instanceRef N_c_out_D1_2))
              )
            )
            (net NlwInverterSignal_N_sum_D2_PT_1_IN0
              (joined
                (portRef OUT (instanceRef NlwInverterBlock_N_sum_D2_PT_1_IN0))
                (portRef IN0 (instanceRef N_sum_D2_PT_1_15))
              )
            )
            (net NlwInverterSignal_N_sum_D2_PT_1_IN1
              (joined
                (portRef OUT (instanceRef NlwInverterBlock_N_sum_D2_PT_1_IN1))
                (portRef IN1 (instanceRef N_sum_D2_PT_1_15))
              )
            )
            (net NlwInverterSignal_N_sum_XOR_IN0
              (joined
                (portRef OUT (instanceRef NlwInverterBlock_N_sum_XOR_IN0))
                (portRef IN0 (instanceRef N_sum_XOR))
              )
            )
          )
      )
    )
  )

  (design ex1
    (cellRef ex1
      (libraryRef ex1_lib)
    )
  )
)