ex1.rpt

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cpldfit:  version E.38                              Xilinx Inc.
                                  Fitter Report
Design Name: ex1                                 Date:  3-11-2008, 10:42AM
Device Used: XC9572-7-PC84
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
2  /72  (  2%) 6   /360  (  1%) 0  /72  (  0%) 5  /69  (  7%) 3  /144 (  2%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    3           3    |  I/O              :     5       58
Output        :    2           2    |  GCK/IO           :     0        3
Bidirectional :    0           0    |  GTS/IO           :     0        2
GCK           :    0           0    |  GSR/IO           :     0        1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total      5           5

MACROCELL RESOURCES:

Total Macrocells Available                    72
Registered Macrocells                          0
Non-registered Macrocell driving I/O           2

GLOBAL RESOURCES:

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 2 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 2 macrocells used (MC).

End of Resource Summary
****************************  Errors and Warnings  *************************

ERROR:Cpld:828 - 'c_out' is assigned to an invalid location ('P52') for this
   device.  This will prevent the design from fitting on the current device.
   'c_out' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sum' is assigned to an invalid location ('P56') for this
   device.  This will prevent the design from fitting on the current device.
   'sum' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'b' is assigned to an invalid location ('P23') for this device.
    This will prevent the design from fitting on the current device. 'b' must be
   reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'c_out' is assigned to an invalid location ('P52') for this
   device.  This will prevent the design from fitting on the current device.
   'c_out' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'sum' is assigned to an invalid location ('P56') for this
   device.  This will prevent the design from fitting on the current device.
   'sum' must be reassigned before attempting a re-fit.
ERROR:Cpld:828 - 'b' is assigned to an invalid location ('P23') for this device.
    This will prevent the design from fitting on the current device. 'b' must be
   reassigned before attempting a re-fit.
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
c_out               3       3       FB4_4   STD  FAST 52   I/O       O
sum                 3       3       FB4_14  STD  FAST 56   I/O       O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
a                                   FB1_13            20   I/O       I
b                                   FB1_16            23   I/O       I
c_in                                FB1_18            24   I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           0           0           0            0         0/0       18   
FB2           0           0           0            0         0/0       17   
FB3           0           0           0            0         0/0       17   
FB4           2           3           3            6         2/0       17   
            ----                                -----       -----     ----- 
              2                                    6         2/0       69   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB1_1         4     I/O     
(unused)              0       0     0   5     FB1_2         1     I/O     
(unused)              0       0     0   5     FB1_3         6     I/O     
(unused)              0       0     0   5     FB1_4         7     I/O     
(unused)              0       0     0   5     FB1_5         2     I/O     
(unused)              0       0     0   5     FB1_6         3     I/O     
(unused)              0       0     0   5     FB1_7         11    I/O     
(unused)              0       0     0   5     FB1_8         5     I/O     
(unused)              0       0     0   5     FB1_9         9     GCK/I/O 
(unused)              0       0     0   5     FB1_10        13    I/O     
(unused)              0       0     0   5     FB1_11        10    GCK/I/O 
(unused)              0       0     0   5     FB1_12        18    I/O     
(unused)              0       0     0   5     FB1_13        20    I/O     I
(unused)              0       0     0   5     FB1_14        12    GCK/I/O 
(unused)              0       0     0   5     FB1_15        14    I/O     
(unused)              0       0     0   5     FB1_16        23    I/O     I
(unused)              0       0     0   5     FB1_17        15    I/O     
(unused)              0       0     0   5     FB1_18        24    I/O     I
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB2_1         63    I/O     
(unused)              0       0     0   5     FB2_2         69    I/O     
(unused)              0       0     0   5     FB2_3         67    I/O     
(unused)              0       0     0   5     FB2_4         68    I/O     
(unused)              0       0     0   5     FB2_5         70    I/O     
(unused)              0       0     0   5     FB2_6         71    I/O     
(unused)              0       0     0   5     FB2_7         76    GTS/I/O 
(unused)              0       0     0   5     FB2_8         72    I/O     
(unused)              0       0     0   5     FB2_9         74    GSR/I/O 
(unused)              0       0     0   5     FB2_10        75    I/O     
(unused)              0       0     0   5     FB2_11        77    GTS/I/O 
(unused)              0       0     0   5     FB2_12        79    I/O     
(unused)              0       0     0   5     FB2_13        80    I/O     
(unused)              0       0     0   5     FB2_14        81    I/O     
(unused)              0       0     0   5     FB2_15        83    I/O     
(unused)              0       0     0   5     FB2_16        82    I/O     
(unused)              0       0     0   5     FB2_17        84    I/O     
(unused)              0       0     0   5     FB2_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin