_primary.vhd

来自「精通VerilogHDL：IC设计核心技术实例详解」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity comp4 is
    port(
        a1              : in     vl_logic_vector(3 downto 0);
        a2              : in     vl_logic_vector(3 downto 0);
        a3              : in     vl_logic_vector(3 downto 0);
        a4              : in     vl_logic_vector(3 downto 0);
        y1              : out    vl_logic_vector(3 downto 0);
        y2              : out    vl_logic_vector(3 downto 0);
        y3              : out    vl_logic_vector(3 downto 0);
        y4              : out    vl_logic_vector(3 downto 0)
    );
end comp4;