_primary.vhd

来自「精通VerilogHDL：IC设计核心技术实例详解」· VHDL 代码 · 共 24 行

library verilog;
use verilog.vl_types.all;
entity mem96x96x16 is
    generic(
        row             : integer := 96;
        col             : integer := 96;
        rowsize         : integer := 7;
        col_size        : integer := 7;
        word_size       : integer := 16
    );
    port(
        cs              : in     vl_logic;
        wr              : in     vl_logic;
        rd              : in     vl_logic;
        din             : in     vl_logic_vector;
        \ROW\           : in     vl_logic_vector;
        \COL\           : in     vl_logic_vector;
        do              : out    vl_logic_vector;
        disp_en         : in     vl_logic;
        disp_row        : in     vl_logic_vector;
        disp_do         : out    vl_logic_vector
    );
end mem96x96x16;