system.h

FPGA开发,DE2开发板上实现,从SD卡读出MP3文件并播放,(即是开发一个简单的MP3播放器)

#define LED_GREEN_DRIVEN_SIM_VALUE 0x0000
#define LED_GREEN_HAS_TRI 0
#define LED_GREEN_HAS_OUT 1
#define LED_GREEN_HAS_IN 0
#define LED_GREEN_CAPTURE 0
#define LED_GREEN_EDGE_TYPE "NONE"
#define LED_GREEN_IRQ_TYPE "NONE"
#define LED_GREEN_FREQ 50000000

/*
 * led_red configuration
 *
 */

#define LED_RED_NAME "/dev/led_red"
#define LED_RED_TYPE "altera_avalon_pio"
#define LED_RED_BASE 0x009000D0
#define LED_RED_SPAN 16
#define LED_RED_DO_TEST_BENCH_WIRING 0
#define LED_RED_DRIVEN_SIM_VALUE 0x0000
#define LED_RED_HAS_TRI 0
#define LED_RED_HAS_OUT 1
#define LED_RED_HAS_IN 0
#define LED_RED_CAPTURE 0
#define LED_RED_EDGE_TYPE "NONE"
#define LED_RED_IRQ_TYPE "NONE"
#define LED_RED_FREQ 50000000

/*
 * button_pio configuration
 *
 */

#define BUTTON_PIO_NAME "/dev/button_pio"
#define BUTTON_PIO_TYPE "altera_avalon_pio"
#define BUTTON_PIO_BASE 0x00900120
#define BUTTON_PIO_SPAN 16
#define BUTTON_PIO_IRQ 5
#define BUTTON_PIO_DO_TEST_BENCH_WIRING 0
#define BUTTON_PIO_DRIVEN_SIM_VALUE 0x0000
#define BUTTON_PIO_HAS_TRI 0
#define BUTTON_PIO_HAS_OUT 0
#define BUTTON_PIO_HAS_IN 1
#define BUTTON_PIO_CAPTURE 1
#define BUTTON_PIO_EDGE_TYPE "FALLING"
#define BUTTON_PIO_IRQ_TYPE "EDGE"
#define BUTTON_PIO_FREQ 50000000

/*
 * switch_pio configuration
 *
 */

#define SWITCH_PIO_NAME "/dev/switch_pio"
#define SWITCH_PIO_TYPE "altera_avalon_pio"
#define SWITCH_PIO_BASE 0x00900130
#define SWITCH_PIO_SPAN 16
#define SWITCH_PIO_DO_TEST_BENCH_WIRING 0
#define SWITCH_PIO_DRIVEN_SIM_VALUE 0x0000
#define SWITCH_PIO_HAS_TRI 0
#define SWITCH_PIO_HAS_OUT 0
#define SWITCH_PIO_HAS_IN 1
#define SWITCH_PIO_CAPTURE 0
#define SWITCH_PIO_EDGE_TYPE "NONE"
#define SWITCH_PIO_IRQ_TYPE "NONE"
#define SWITCH_PIO_FREQ 50000000

/*
 * SEG7_Display configuration
 *
 */

#define SEG7_DISPLAY_NAME "/dev/SEG7_Display"
#define SEG7_DISPLAY_TYPE "user_logic_SEG7_LUT_8"
#define SEG7_DISPLAY_BASE 0x00900028
#define SEG7_DISPLAY_SPAN 4

/*
 * sram_0 configuration
 *
 */

#define SRAM_0_NAME "/dev/sram_0"
#define SRAM_0_TYPE "user_logic_SRAM_16Bits_512K"
#define SRAM_0_BASE 0x00980000
#define SRAM_0_SPAN 524288

/*
 * I2C_0 configuration
 *
 */

#define I2C_0_NAME "/dev/I2C_0"
#define I2C_0_TYPE "user_logic_Open_I2C"
#define I2C_0_BASE 0x00900100
#define I2C_0_SPAN 32
#define I2C_0_IRQ 6

/*
 * epcs_controller configuration
 *
 */

#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"
#define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"
#define EPCS_CONTROLLER_BASE 0x00900800
#define EPCS_CONTROLLER_SPAN 2048
#define EPCS_CONTROLLER_IRQ 7
#define EPCS_CONTROLLER_DATABITS 8
#define EPCS_CONTROLLER_TARGETCLOCK 20
#define EPCS_CONTROLLER_CLOCKUNITS "MHz"
#define EPCS_CONTROLLER_CLOCKMULT 1000000
#define EPCS_CONTROLLER_NUMSLAVES 1
#define EPCS_CONTROLLER_ISMASTER 1
#define EPCS_CONTROLLER_CLOCKPOLARITY 0
#define EPCS_CONTROLLER_CLOCKPHASE 0
#define EPCS_CONTROLLER_LSBFIRST 0
#define EPCS_CONTROLLER_EXTRADELAY 1
#define EPCS_CONTROLLER_TARGETSSDELAY 100
#define EPCS_CONTROLLER_DELAYUNITS "us"
#define EPCS_CONTROLLER_DELAYMULT "1e-006"
#define EPCS_CONTROLLER_PREFIX "epcs_"
#define EPCS_CONTROLLER_REGISTER_OFFSET 0x200
#define EPCS_CONTROLLER_CLOCKUNIT "kHz"
#define EPCS_CONTROLLER_DELAYUNIT "us"

/*
 * ISP1362 configuration
 *
 */

#define ISP1362_NAME "/dev/ISP1362"
#define ISP1362_TYPE "altera_avalon_user_defined_interface"
#define ISP1362_BASE 0x00900080
#define ISP1362_SPAN 16
#define ISP1362_IRQ 4
#define ISP1362_IMPORTED_WAIT 0
#define ISP1362_NIOS_GEN_WAITS 1
#define ISP1362_SIMULATE_IMPORTED_HDL 1
#define ISP1362_PORT_TYPE "Avalon Slave"
#define ISP1362_HDL_IMPORT 1
#define ISP1362_TIMING_UNITS "ns"
#define ISP1362_UNIT_MULTIPLIER 1
#define ISP1362_SETUP_VALUE 200
#define ISP1362_HOLD_VALUE 200
#define ISP1362_WAIT_VALUE 100
#define ISP1362_ADDRESS_WIDTH 32
#define ISP1362_MODULE_LIST ""
#define ISP1362_SHOW_STREAMING 0
#define ISP1362_SHOW_LATENCY 0
#define ISP1362_TECHNOLOGY "User Logic"
#define ISP1362_FILE_COUNT 1
#define ISP1362_PORT_COUNT 24
#define ISP1362_COMPONENT_DESC "ISP1362"
#define ISP1362_MODULE_NAME "ISP1362_IF"

/*
 * DM9000A configuration
 *
 */

#define DM9000A_NAME "/dev/DM9000A"
#define DM9000A_TYPE "user_logic_DM9000A"
#define DM9000A_BASE 0x00900090
#define DM9000A_SPAN 8
#define DM9000A_IRQ 8

/*
 * SD_DAT configuration
 *
 */

#define SD_DAT_NAME "/dev/SD_DAT"
#define SD_DAT_TYPE "altera_avalon_pio"
#define SD_DAT_BASE 0x009000A0
#define SD_DAT_SPAN 16
#define SD_DAT_DO_TEST_BENCH_WIRING 0
#define SD_DAT_DRIVEN_SIM_VALUE 0x0000
#define SD_DAT_HAS_TRI 1
#define SD_DAT_HAS_OUT 0
#define SD_DAT_HAS_IN 0
#define SD_DAT_CAPTURE 0
#define SD_DAT_EDGE_TYPE "NONE"
#define SD_DAT_IRQ_TYPE "NONE"
#define SD_DAT_FREQ 50000000

/*
 * SD_CMD configuration
 *
 */

#define SD_CMD_NAME "/dev/SD_CMD"
#define SD_CMD_TYPE "altera_avalon_pio"
#define SD_CMD_BASE 0x009000B0
#define SD_CMD_SPAN 16
#define SD_CMD_DO_TEST_BENCH_WIRING 0
#define SD_CMD_DRIVEN_SIM_VALUE 0x0000
#define SD_CMD_HAS_TRI 1
#define SD_CMD_HAS_OUT 0
#define SD_CMD_HAS_IN 0
#define SD_CMD_CAPTURE 0
#define SD_CMD_EDGE_TYPE "NONE"
#define SD_CMD_IRQ_TYPE "NONE"
#define SD_CMD_FREQ 50000000

/*
 * SD_CLK configuration
 *
 */

#define SD_CLK_NAME "/dev/SD_CLK"
#define SD_CLK_TYPE "altera_avalon_pio"
#define SD_CLK_BASE 0x009000E0
#define SD_CLK_SPAN 16
#define SD_CLK_DO_TEST_BENCH_WIRING 0
#define SD_CLK_DRIVEN_SIM_VALUE 0x0000
#define SD_CLK_HAS_TRI 0
#define SD_CLK_HAS_OUT 1
#define SD_CLK_HAS_IN 0
#define SD_CLK_CAPTURE 0
#define SD_CLK_EDGE_TYPE "NONE"
#define SD_CLK_IRQ_TYPE "NONE"
#define SD_CLK_FREQ 50000000

/*
 * Audio_0 configuration
 *
 */

#define AUDIO_0_NAME "/dev/Audio_0"
#define AUDIO_0_TYPE "altera_avalon_user_defined_interface"
#define AUDIO_0_BASE 0x0090002C
#define AUDIO_0_SPAN 4
#define AUDIO_0_IMPORTED_WAIT 0
#define AUDIO_0_NIOS_GEN_WAITS 1
#define AUDIO_0_SIMULATE_IMPORTED_HDL 1
#define AUDIO_0_PORT_TYPE "Avalon Slave"
#define AUDIO_0_HDL_IMPORT 1
#define AUDIO_0_TIMING_UNITS "ns"
#define AUDIO_0_UNIT_MULTIPLIER 1
#define AUDIO_0_SETUP_VALUE 20
#define AUDIO_0_HOLD_VALUE 02
#define AUDIO_0_WAIT_VALUE 20
#define AUDIO_0_ADDRESS_WIDTH 32
#define AUDIO_0_MODULE_LIST ""
#define AUDIO_0_SHOW_STREAMING 0
#define AUDIO_0_SHOW_LATENCY 0
#define AUDIO_0_TECHNOLOGY "User Logic"
#define AUDIO_0_FILE_COUNT 3
#define AUDIO_0_PORT_COUNT 9
#define AUDIO_0_COMPONENT_DESC "Audio"
#define AUDIO_0_MODULE_NAME "AUDIO_DAC_FIFO"

/*
 * AUD_FULL configuration
 *
 */

#define AUD_FULL_NAME "/dev/AUD_FULL"
#define AUD_FULL_TYPE "altera_avalon_pio"
#define AUD_FULL_BASE 0x009000F0
#define AUD_FULL_SPAN 16
#define AUD_FULL_DO_TEST_BENCH_WIRING 0
#define AUD_FULL_DRIVEN_SIM_VALUE 0x0000
#define AUD_FULL_HAS_TRI 0
#define AUD_FULL_HAS_OUT 0
#define AUD_FULL_HAS_IN 1
#define AUD_FULL_CAPTURE 0
#define AUD_FULL_EDGE_TYPE "NONE"
#define AUD_FULL_IRQ_TYPE "NONE"
#define AUD_FULL_FREQ 50000000

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK TIMER_0
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM_0
#define ALT_RODATA_DEVICE     SDRAM_0
#define ALT_RWDATA_DEVICE     SDRAM_0
#define ALT_EXCEPTIONS_DEVICE SDRAM_0
#define ALT_RESET_DEVICE      EPCS_CONTROLLER


#endif /* __SYSTEM_H_ */