all_traffic.map.qmsg

一个简单的交通灯程序(包括验证,主程序,和译码程序),在ALTER DE2板上实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 03 14:10:06 2007 " "Info: Processing started: Tue Apr 03 14:10:06 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off All_traffic -c All_traffic " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off All_traffic -c All_traffic" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "All_traffic.bdf 1 1 " "Info: Using design file All_traffic.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 All_traffic " "Info: Found entity 1: All_traffic" {  } { { "All_traffic.bdf" "" { Schematic "E:/FPGA/EDA4.3/All traffic/All_traffic.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "All_traffic " "Info: Elaborating entity \"All_traffic\" for the top level hierarchy" {  } {  } 0}
{ "Error" "EGDFX_ILLEGAL_WIRE_OR_BUS_NAME" "pin ewa\[6...0\] " "Error: Illegal wire or bus name \"ewa\[6...0\]\" of type pin " {  } { { "All_traffic.bdf" "" { Schematic "E:/FPGA/EDA4.3/All traffic/All_traffic.bdf" { { 192 832 1008 208 "ewa\[6...0\]" "" } } } }  } 0}
{ "Error" "EGDFX_ILLEGAL_WIRE_OR_BUS_NAME" "pin ewb\[6...0\] " "Error: Illegal wire or bus name \"ewb\[6...0\]\" of type pin " {  } { { "All_traffic.bdf" "" { Schematic "E:/FPGA/EDA4.3/All traffic/All_traffic.bdf" { { 248 840 1016 264 "ewb\[6...0\]" "" } } } }  } 0}
{ "Error" "EGDFX_ILLEGAL_WIRE_OR_BUS_NAME" "pin sna\[6...0\] " "Error: Illegal wire or bus name \"sna\[6...0\]\" of type pin " {  } { { "All_traffic.bdf" "" { Schematic "E:/FPGA/EDA4.3/All traffic/All_traffic.bdf" { { 336 848 1024 352 "sna\[6...0\]" "" } } } }  } 0}
{ "Error" "EGDFX_ILLEGAL_WIRE_OR_BUS_NAME" "pin snb\[6...0\] " "Error: Illegal wire or bus name \"snb\[6...0\]\" of type pin " {  } { { "All_traffic.bdf" "" { Schematic "E:/FPGA/EDA4.3/All traffic/All_traffic.bdf" { { 448 864 1040 464 "snb\[6...0\]" "" } } } }  } 0}
{ "Error" "EGDFX_ILLEGAL_WIRE_OR_BUS_NAME" "signal ewa\[6...0\] " "Error: Illegal wire or bus name \"ewa\[6...0\]\" of type signal " {  } { { "All_traffic.bdf" "" { Schematic "E:/FPGA/EDA4.3/All traffic/All_traffic.bdf" { { 56 672 760 72 "ewa\[6...0\]" "" } } } }  } 0}
{ "Error" "EGDFX_ILLEGAL_WIRE_OR_BUS_NAME" "signal ewb\[6...0\] " "Error: Illegal wire or bus name \"ewb\[6...0\]\" of type signal " {  } { { "All_traffic.bdf" "" { Schematic "E:/FPGA/EDA4.3/All traffic/All_traffic.bdf" { { 192 672 760 208 "ewb\[6...0\]" "" } } } }  } 0}
{ "Error" "EGDFX_ILLEGAL_WIRE_OR_BUS_NAME" "signal sna\[6...0\] " "Error: Illegal wire or bus name \"sna\[6...0\]\" of type signal " {  } { { "All_traffic.bdf" "" { Schematic "E:/FPGA/EDA4.3/All traffic/All_traffic.bdf" { { 328 680 768 344 "sna\[6...0\]" "" } } } }  } 0}
{ "Error" "EGDFX_ILLEGAL_WIRE_OR_BUS_NAME" "signal snb\[6...0\] " "Error: Illegal wire or bus name \"snb\[6...0\]\" of type signal " {  } { { "All_traffic.bdf" "" { Schematic "E:/FPGA/EDA4.3/All traffic/All_traffic.bdf" { { 456 680 792 472 "snb\[6...0\]" "" } } } }  } 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 9 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Tue Apr 03 14:10:06 2007 " "Error: Processing ended: Tue Apr 03 14:10:06 2007" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}