📄 traffic.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity traffic is
port(clk,urgency:in std_logic;
east_west:buffer std_logic_vector(7 downto 0);
south_north:buffer std_logic_vector(7 downto 0);
led:buffer std_logic_vector(5 downto 0);
east_westa : buffer std_logic_vector(3downto 0);
east_westb : buffer std_logic_vector(3 downto 0);
south_northa : buffer std_logic_vector(3 downto 0);
south_northb : buffer std_logic_vector(3 downto 0) );
end traffic;
architecture arch of traffic is
begin
process(clk,urgency)
begin
if urgency='1' then
led<="100001";
elsif(clk'event and clk='1') then
if(east_west=6 and south_north=1)then
east_west<="00000101";
south_north<="00000101";
led<="100010";
elsif(east_west=1 and south_north=1 and led(5)='1')then
East_west<="01000000";
South_north<="01000101";
Led<="001001";
Elsif(east_west=1 and south_north=6) then
East_west<="00000101";
South_north<="00000101";
Led<="010001";
Elsif((east_west=1 and south_north=1 and led(0)='1') or east_west=0) then
East_west<="01000101";
South_north<="01000000";
Led<="100100";
Elsif(east_west(3 downto 0)="0000") then
East_west<=east_west-7;
South_north<=south_north-1;
Elsif(south_north(3 downto 0)="0000") then
East_west<=east_west-1;
South_north<=south_north-7;
Else
East_west<=east_west-1;
South_north<=south_north-1;
End if;
End if;
east_westa <= east_west(3 downto 0);
east_westb <= east_west(7 downto 4) ;
south_northa <= south_north(3 downto 0);
south_northb<= south_north(7 downto 4);
End process;
End arch;
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