📄 cnt.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt is
port(clk: in std_logic;
cout: out std_logic);
end cnt;
architecture behav of cnt is
begin
process(clk)
variable q: std_logic_vector(25 downto 0);
begin
if clk'event and clk='1' then
q:=q+1;
end if;
if q="1100110111111110011000000" then cout<='1';
else cout<='0';
end if;
end process;
end behav;
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