📄 decl7s.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECL7S IS
PORT (A :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END;
ARCHITECTURE ONE OF DECL7S IS
BEGIN
PROCESS(A)
BEGIN
CASE A IS
WHEN "0000" => LED7S <="1000000";
WHEN "0001" => LED7S <="1111001";
WHEN "0010" => LED7S <="0100100";
WHEN "0011" => LED7S <="0110000";
WHEN "0100" => LED7S <="0011001";
WHEN "0101" => LED7S <="0010010";
WHEN "0110" => LED7S <="0000010";
WHEN "0111" => LED7S <="1111000";
WHEN "1000" => LED7S <="0000000";
WHEN "1001" => LED7S <="0010000";
when others => null;
end case;
end process;
end;
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