traffic.tan.qmsg

一个简单的交通灯程序(包括验证,主程序,和译码程序),在ALTER DE2板上实现

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register east_west\[4\]~reg0 register led\[5\]~reg0 135.5 MHz 7.38 ns Internal " "Info: Clock \"clk\" has Internal fmax of 135.5 MHz between source register \"east_west\[4\]~reg0\" and destination register \"led\[5\]~reg0\" (period= 7.38 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.112 ns + Longest register register " "Info: + Longest register to register delay is 7.112 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns east_west\[4\]~reg0 1 REG LCFF_X40_Y26_N23 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y26_N23; Fanout = 5; REG Node = 'east_west\[4\]~reg0'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[4]~reg0 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.113 ns) + CELL(0.636 ns) 1.749 ns east_west\[7\]~914 2 COMB LCCOMB_X42_Y26_N20 1 " "Info: 2: + IC(1.113 ns) + CELL(0.636 ns) = 1.749 ns; Loc. = LCCOMB_X42_Y26_N20; Fanout = 1; COMB Node = 'east_west\[7\]~914'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "1.749 ns" { east_west[4]~reg0 east_west[7]~914 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.352 ns) + CELL(0.378 ns) 2.479 ns east_west\[7\]~915 3 COMB LCCOMB_X42_Y26_N16 5 " "Info: 3: + IC(0.352 ns) + CELL(0.378 ns) = 2.479 ns; Loc. = LCCOMB_X42_Y26_N16; Fanout = 5; COMB Node = 'east_west\[7\]~915'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "0.730 ns" { east_west[7]~914 east_west[7]~915 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.378 ns) 3.255 ns process0~228 4 COMB LCCOMB_X42_Y26_N0 3 " "Info: 4: + IC(0.398 ns) + CELL(0.378 ns) = 3.255 ns; Loc. = LCCOMB_X42_Y26_N0; Fanout = 3; COMB Node = 'process0~228'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "0.776 ns" { east_west[7]~915 process0~228 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.210 ns) 3.831 ns process0~5 5 COMB LCCOMB_X42_Y26_N6 6 " "Info: 5: + IC(0.366 ns) + CELL(0.210 ns) = 3.831 ns; Loc. = LCCOMB_X42_Y26_N6; Fanout = 6; COMB Node = 'process0~5'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "0.576 ns" { process0~228 process0~5 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.158 ns) + CELL(0.636 ns) 5.625 ns led\[5\]~576 6 COMB LCCOMB_X40_Y26_N0 1 " "Info: 6: + IC(1.158 ns) + CELL(0.636 ns) = 5.625 ns; Loc. = LCCOMB_X40_Y26_N0; Fanout = 1; COMB Node = 'led\[5\]~576'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "1.794 ns" { process0~5 led[5]~576 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.999 ns) + CELL(0.378 ns) 7.002 ns led\[5\]~577 7 COMB LCCOMB_X44_Y26_N8 1 " "Info: 7: + IC(0.999 ns) + CELL(0.378 ns) = 7.002 ns; Loc. = LCCOMB_X44_Y26_N8; Fanout = 1; COMB Node = 'led\[5\]~577'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "1.377 ns" { led[5]~576 led[5]~577 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 7.112 ns led\[5\]~reg0 8 REG LCFF_X44_Y26_N9 4 " "Info: 8: + IC(0.000 ns) + CELL(0.110 ns) = 7.112 ns; Loc. = LCFF_X44_Y26_N9; Fanout = 4; REG Node = 'led\[5\]~reg0'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "0.110 ns" { led[5]~577 led[5]~reg0 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns 38.33 % " "Info: Total cell delay = 2.726 ns ( 38.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.386 ns 61.67 % " "Info: Total interconnect delay = 4.386 ns ( 61.67 % )" {  } {  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "7.112 ns" { east_west[4]~reg0 east_west[7]~914 east_west[7]~915 process0~228 process0~5 led[5]~576 led[5]~577 led[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.112 ns" { east_west[4]~reg0 east_west[7]~914 east_west[7]~915 process0~228 process0~5 led[5]~576 led[5]~577 led[5]~reg0 } { 0.000ns 1.113ns 0.352ns 0.398ns 0.366ns 1.158ns 0.999ns 0.000ns } { 0.000ns 0.636ns 0.378ns 0.378ns 0.210ns 0.636ns 0.378ns 0.110ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.119 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.119 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'clk~clkctrl'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.201 ns) + CELL(0.679 ns) 3.119 ns led\[5\]~reg0 3 REG LCFF_X44_Y26_N9 4 " "Info: 3: + IC(1.201 ns) + CELL(0.679 ns) = 3.119 ns; Loc. = LCFF_X44_Y26_N9; Fanout = 4; REG Node = 'led\[5\]~reg0'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "1.880 ns" { clk~clkctrl led[5]~reg0 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 57.04 % " "Info: Total cell delay = 1.779 ns ( 57.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.340 ns 42.96 % " "Info: Total interconnect delay = 1.340 ns ( 42.96 % )" {  } {  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.119 ns" { clk clk~clkctrl led[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.119 ns" { clk clk~combout clk~clkctrl led[5]~reg0 } { 0.000ns 0.000ns 0.139ns 1.201ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.117 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.117 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'clk~clkctrl'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.679 ns) 3.117 ns east_west\[4\]~reg0 3 REG LCFF_X40_Y26_N23 5 " "Info: 3: + IC(1.199 ns) + CELL(0.679 ns) = 3.117 ns; Loc. = LCFF_X40_Y26_N23; Fanout = 5; REG Node = 'east_west\[4\]~reg0'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "1.878 ns" { clk~clkctrl east_west[4]~reg0 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 57.07 % " "Info: Total cell delay = 1.779 ns ( 57.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.338 ns 42.93 % " "Info: Total interconnect delay = 1.338 ns ( 42.93 % )" {  } {  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.117 ns" { clk clk~clkctrl east_west[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.117 ns" { clk clk~combout clk~clkctrl east_west[4]~reg0 } { 0.000ns 0.000ns 0.139ns 1.199ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.119 ns" { clk clk~clkctrl led[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.119 ns" { clk clk~combout clk~clkctrl led[5]~reg0 } { 0.000ns 0.000ns 0.139ns 1.201ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.117 ns" { clk clk~clkctrl east_west[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.117 ns" { clk clk~combout clk~clkctrl east_west[4]~reg0 } { 0.000ns 0.000ns 0.139ns 1.199ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "7.112 ns" { east_west[4]~reg0 east_west[7]~914 east_west[7]~915 process0~228 process0~5 led[5]~576 led[5]~577 led[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.112 ns" { east_west[4]~reg0 east_west[7]~914 east_west[7]~915 process0~228 process0~5 led[5]~576 led[5]~577 led[5]~reg0 } { 0.000ns 1.113ns 0.352ns 0.398ns 0.366ns 1.158ns 0.999ns 0.000ns } { 0.000ns 0.636ns 0.378ns 0.378ns 0.210ns 0.636ns 0.378ns 0.110ns } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.119 ns" { clk clk~clkctrl led[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.119 ns" { clk clk~combout clk~clkctrl led[5]~reg0 } { 0.000ns 0.000ns 0.139ns 1.201ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.117 ns" { clk clk~clkctrl east_west[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.117 ns" { clk clk~combout clk~clkctrl east_west[4]~reg0 } { 0.000ns 0.000ns 0.139ns 1.199ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "south_north\[0\]~reg0 urgency clk 1.859 ns register " "Info: tsu for register \"south_north\[0\]~reg0\" (data pin = \"urgency\", clock pin = \"clk\") is 1.859 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.019 ns + Longest pin register " "Info: + Longest pin to register delay is 5.019 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns urgency 1 PIN PIN_P1 17 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P1; Fanout = 17; PIN Node = 'urgency'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { urgency } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.047 ns) + CELL(0.872 ns) 5.019 ns south_north\[0\]~reg0 2 REG LCFF_X43_Y26_N23 7 " "Info: 2: + IC(3.047 ns) + CELL(0.872 ns) = 5.019 ns; Loc. = LCFF_X43_Y26_N23; Fanout = 7; REG Node = 'south_north\[0\]~reg0'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.919 ns" { urgency south_north[0]~reg0 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.972 ns 39.29 % " "Info: Total cell delay = 1.972 ns ( 39.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.047 ns 60.71 % " "Info: Total interconnect delay = 3.047 ns ( 60.71 % )" {  } {  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "5.019 ns" { urgency south_north[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.019 ns" { urgency urgency~combout south_north[0]~reg0 } { 0.000ns 0.000ns 3.047ns } { 0.000ns 1.100ns 0.872ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.120 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.120 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'clk~clkctrl'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.202 ns) + CELL(0.679 ns) 3.120 ns south_north\[0\]~reg0 3 REG LCFF_X43_Y26_N23 7 " "Info: 3: + IC(1.202 ns) + CELL(0.679 ns) = 3.120 ns; Loc. = LCFF_X43_Y26_N23; Fanout = 7; REG Node = 'south_north\[0\]~reg0'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "1.881 ns" { clk~clkctrl south_north[0]~reg0 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 57.02 % " "Info: Total cell delay = 1.779 ns ( 57.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.341 ns 42.98 % " "Info: Total interconnect delay = 1.341 ns ( 42.98 % )" {  } {  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.120 ns" { clk clk~clkctrl south_north[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.120 ns" { clk clk~combout clk~clkctrl south_north[0]~reg0 } { 0.000ns 0.000ns 0.139ns 1.202ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "5.019 ns" { urgency south_north[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.019 ns" { urgency urgency~combout south_north[0]~reg0 } { 0.000ns 0.000ns 3.047ns } { 0.000ns 1.100ns 0.872ns } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.120 ns" { clk clk~clkctrl south_north[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.120 ns" { clk clk~combout clk~clkctrl south_north[0]~reg0 } { 0.000ns 0.000ns 0.139ns 1.202ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk east_west\[1\] east_west\[1\]~reg0 10.348 ns register " "Info: tco from clock \"clk\" to destination pin \"east_west\[1\]\" through register \"east_west\[1\]~reg0\" is 10.348 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.118 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.118 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'clk~clkctrl'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.679 ns) 3.118 ns east_west\[1\]~reg0 3 REG LCFF_X41_Y26_N1 9 " "Info: 3: + IC(1.200 ns) + CELL(0.679 ns) = 3.118 ns; Loc. = LCFF_X41_Y26_N1; Fanout = 9; REG Node = 'east_west\[1\]~reg0'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "1.879 ns" { clk~clkctrl east_west[1]~reg0 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 57.06 % " "Info: Total cell delay = 1.779 ns ( 57.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.339 ns 42.94 % " "Info: Total interconnect delay = 1.339 ns ( 42.94 % )" {  } {  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.118 ns" { clk clk~clkctrl east_west[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.118 ns" { clk clk~combout clk~clkctrl east_west[1]~reg0 } { 0.000ns 0.000ns 0.139ns 1.200ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.920 ns + Longest register pin " "Info: + Longest register to pin delay is 6.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns east_west\[1\]~reg0 1 REG LCFF_X41_Y26_N1 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X41_Y26_N1; Fanout = 9; REG Node = 'east_west\[1\]~reg0'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[1]~reg0 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.019 ns) + CELL(2.901 ns) 6.920 ns east_west\[1\] 2 PIN PIN_H2 0 " "Info: 2: + IC(4.019 ns) + CELL(2.901 ns) = 6.920 ns; Loc. = PIN_H2; Fanout = 0; PIN Node = 'east_west\[1\]'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "6.920 ns" { east_west[1]~reg0 east_west[1] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.901 ns 41.92 % " "Info: Total cell delay = 2.901 ns ( 41.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.019 ns 58.08 % " "Info: Total interconnect delay = 4.019 ns ( 58.08 % )" {  } {  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "6.920 ns" { east_west[1]~reg0 east_west[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.920 ns" { east_west[1]~reg0 east_west[1] } { 0.000ns 4.019ns } { 0.000ns 2.901ns } } }  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.118 ns" { clk clk~clkctrl east_west[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.118 ns" { clk clk~combout clk~clkctrl east_west[1]~reg0 } { 0.000ns 0.000ns 0.139ns 1.200ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "6.920 ns" { east_west[1]~reg0 east_west[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.920 ns" { east_west[1]~reg0 east_west[1] } { 0.000ns 4.019ns } { 0.000ns 2.901ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "east_west\[0\]~reg0 urgency clk -1.334 ns register " "Info: th for register \"east_west\[0\]~reg0\" (data pin = \"urgency\", clock pin = \"clk\") is -1.334 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.118 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.118 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'clk~clkctrl'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.679 ns) 3.118 ns east_west\[0\]~reg0 3 REG LCFF_X41_Y26_N15 9 " "Info: 3: + IC(1.200 ns) + CELL(0.679 ns) = 3.118 ns; Loc. = LCFF_X41_Y26_N15; Fanout = 9; REG Node = 'east_west\[0\]~reg0'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "1.879 ns" { clk~clkctrl east_west[0]~reg0 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 57.06 % " "Info: Total cell delay = 1.779 ns ( 57.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.339 ns 42.94 % " "Info: Total interconnect delay = 1.339 ns ( 42.94 % )" {  } {  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.118 ns" { clk clk~clkctrl east_west[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.118 ns" { clk clk~combout clk~clkctrl east_west[0]~reg0 } { 0.000ns 0.000ns 0.139ns 1.200ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.211 ns + " "Info: + Micro hold delay of destination is 0.211 ns" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.663 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns urgency 1 PIN PIN_P1 17 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P1; Fanout = 17; PIN Node = 'urgency'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { urgency } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.691 ns) + CELL(0.872 ns) 4.663 ns east_west\[0\]~reg0 2 REG LCFF_X41_Y26_N15 9 " "Info: 2: + IC(2.691 ns) + CELL(0.872 ns) = 4.663 ns; Loc. = LCFF_X41_Y26_N15; Fanout = 9; REG Node = 'east_west\[0\]~reg0'" {  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.563 ns" { urgency east_west[0]~reg0 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.972 ns 42.29 % " "Info: Total cell delay = 1.972 ns ( 42.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.691 ns 57.71 % " "Info: Total interconnect delay = 2.691 ns ( 57.71 % )" {  } {  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "4.663 ns" { urgency east_west[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.663 ns" { urgency urgency~combout east_west[0]~reg0 } { 0.000ns 0.000ns 2.691ns } { 0.000ns 1.100ns 0.872ns } } }  } 0}  } { { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "3.118 ns" { clk clk~clkctrl east_west[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.118 ns" { clk clk~combout clk~clkctrl east_west[0]~reg0 } { 0.000ns 0.000ns 0.139ns 1.200ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "4.663 ns" { urgency east_west[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.663 ns" { urgency urgency~combout east_west[0]~reg0 } { 0.000ns 0.000ns 2.691ns } { 0.000ns 1.100ns 0.872ns } } }  } 0}