📄 traffic.fit.qmsg

📁 一个简单的交通灯程序(包括验证,主程序,和译码程序),在ALTER DE2板上实现
💻 QMSG
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{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "40 40 " "Info: No exact pin location assignment(s) for 40 pins of 40 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_west\[0\] " "Info: Pin east_west\[0\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[0\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[0] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_west\[1\] " "Info: Pin east_west\[1\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[1\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[1] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_west\[2\] " "Info: Pin east_west\[2\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[2\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[2] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_west\[3\] " "Info: Pin east_west\[3\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[3\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[3] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_west\[4\] " "Info: Pin east_west\[4\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[4\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[4] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_west\[5\] " "Info: Pin east_west\[5\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[5\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[5] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_west\[6\] " "Info: Pin east_west\[6\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[6\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[6] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_west\[7\] " "Info: Pin east_west\[7\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[7\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[7] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_north\[0\] " "Info: Pin south_north\[0\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_north\[0\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_north[0] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_north[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_north\[1\] " "Info: Pin south_north\[1\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_north\[1\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_north[1] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_north[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_north\[2\] " "Info: Pin south_north\[2\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_north\[2\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_north[2] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_north[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_north\[3\] " "Info: Pin south_north\[3\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_north\[3\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_north[3] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_north[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_north\[4\] " "Info: Pin south_north\[4\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_north\[4\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_north[4] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_north[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_north\[5\] " "Info: Pin south_north\[5\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_north\[5\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_north[5] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_north[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_north\[6\] " "Info: Pin south_north\[6\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_north\[6\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_north[6] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_north[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_north\[7\] " "Info: Pin south_north\[7\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_north\[7\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_north[7] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_north[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led\[0\] " "Info: Pin led\[0\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led\[0\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { led[0] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { led[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led\[1\] " "Info: Pin led\[1\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led\[1\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { led[1] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { led[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led\[2\] " "Info: Pin led\[2\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led\[2\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { led[2] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { led[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led\[3\] " "Info: Pin led\[3\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led\[3\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { led[3] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { led[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led\[4\] " "Info: Pin led\[4\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led\[4\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { led[4] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { led[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led\[5\] " "Info: Pin led\[5\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led\[5\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { led[5] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { led[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_westa\[0\] " "Info: Pin east_westa\[0\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_westa\[0\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_westa[0] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_westa[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_westa\[1\] " "Info: Pin east_westa\[1\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_westa\[1\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_westa[1] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_westa[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_westa\[2\] " "Info: Pin east_westa\[2\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_westa\[2\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_westa[2] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_westa[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_westa\[3\] " "Info: Pin east_westa\[3\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_westa\[3\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_westa[3] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_westa[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_westb\[0\] " "Info: Pin east_westb\[0\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 10 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_westb\[0\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_westb[0] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_westb[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_westb\[1\] " "Info: Pin east_westb\[1\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 10 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_westb\[1\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_westb[1] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_westb[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_westb\[2\] " "Info: Pin east_westb\[2\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 10 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_westb\[2\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_westb[2] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_westb[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "east_westb\[3\] " "Info: Pin east_westb\[3\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 10 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_westb\[3\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_westb[3] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_westb[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_northa\[0\] " "Info: Pin south_northa\[0\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 11 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_northa\[0\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_northa[0] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_northa[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_northa\[1\] " "Info: Pin south_northa\[1\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 11 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_northa\[1\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_northa[1] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_northa[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_northa\[2\] " "Info: Pin south_northa\[2\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 11 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_northa\[2\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_northa[2] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_northa[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_northa\[3\] " "Info: Pin south_northa\[3\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 11 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_northa\[3\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_northa[3] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_northa[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_northb\[0\] " "Info: Pin south_northb\[0\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 12 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_northb\[0\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_northb[0] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_northb[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_northb\[1\] " "Info: Pin south_northb\[1\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 12 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_northb\[1\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_northb[1] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_northb[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_northb\[2\] " "Info: Pin south_northb\[2\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 12 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_northb\[2\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_northb[2] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_northb[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "south_northb\[3\] " "Info: Pin south_northb\[3\] not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 12 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_northb\[3\]" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_northb[3] } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_northb[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { clk } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "urgency " "Info: Pin urgency not assigned to an exact location on the device" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "urgency" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { urgency } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { urgency } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN P2 (CLK2, LVDSCLK1p, Input)) " "Info: Automatically promoted node clk (placed in PIN P2 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0}  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { clk } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "urgency (placed in PIN P1 (CLK3, LVDSCLK1n, Input)) " "Info: Automatically promoted node urgency (placed in PIN P1 (CLK3, LVDSCLK1n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" {  } {  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "east_west\[7\]~reg0 " "Info: Destination node east_west\[7\]~reg0" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[7\]~reg0" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[7]~reg0 } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[7]~reg0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "east_west\[6\]~reg0 " "Info: Destination node east_west\[6\]~reg0" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[6\]~reg0" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[6]~reg0 } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[6]~reg0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "east_west\[5\]~reg0 " "Info: Destination node east_west\[5\]~reg0" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[5\]~reg0" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[5]~reg0 } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[5]~reg0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "east_west\[4\]~reg0 " "Info: Destination node east_west\[4\]~reg0" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[4\]~reg0" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[4]~reg0 } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[4]~reg0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "east_west\[3\]~reg0 " "Info: Destination node east_west\[3\]~reg0" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[3\]~reg0" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[3]~reg0 } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[3]~reg0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "east_west\[2\]~reg0 " "Info: Destination node east_west\[2\]~reg0" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[2\]~reg0" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[2]~reg0 } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[2]~reg0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "east_west\[1\]~reg0 " "Info: Destination node east_west\[1\]~reg0" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[1\]~reg0" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[1]~reg0 } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[1]~reg0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "east_west\[0\]~reg0 " "Info: Destination node east_west\[0\]~reg0" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "east_west\[0\]~reg0" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { east_west[0]~reg0 } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { east_west[0]~reg0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "south_north\[7\]~reg0 " "Info: Destination node south_north\[7\]~reg0" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_north\[7\]~reg0" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_north[7]~reg0 } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_north[7]~reg0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "south_north\[6\]~reg0 " "Info: Destination node south_north\[6\]~reg0" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "south_north\[6\]~reg0" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { south_north[6]~reg0 } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { south_north[6]~reg0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0}  } {  } 0}  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "urgency" } } } } { "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" "" { Report "E:/FPGA/EDA4.3/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/FPGA/EDA4.3/traffic/db/traffic.quartus_db" { Floorplan "E:/FPGA/EDA4.3/traffic/" "" "" { urgency } "NODE_NAME" } "" } } { "E:/FPGA/EDA4.3/traffic/traffic.fld" "" { Floorplan "E:/FPGA/EDA4.3/traffic/traffic.fld" "" "" { urgency } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
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