traffic.map.rpt

一个简单的交通灯程序(包括验证,主程序,和译码程序),在ALTER DE2板上实现

; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path       ;
+----------------------------------+-----------------+-----------------+------------------------------------+
; traffic.vhd                      ; yes             ; User VHDL File  ; E:/FPGA/EDA4.3/traffic/traffic.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total combinational functions               ; 57    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 19    ;
;     -- 3 input functions                    ; 10    ;
;     -- <=2 input functions                  ; 28    ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 43    ;
;     -- arithmetic mode                      ; 14    ;
; Total registers                             ; 22    ;
; I/O pins                                    ; 40    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 22    ;
; Total fan-out                               ; 268   ;
; Average fan-out                             ; 2.25  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |traffic                   ; 57 (57)           ; 22 (22)      ; 0           ; 0            ; 0       ; 0         ; 40   ; 0            ; |traffic            ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 22    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 6     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 20    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; led[0]~reg0                            ; 2       ;
; led[5]~reg0                            ; 4       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |traffic|led[4]~reg0         ;
; 5:1                ; 12 bits   ; 36 LEs        ; 36 LEs               ; 0 LEs                  ; Yes        ; |traffic|east_west[1]~reg0   ;
; 5:1                ; 4 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |traffic|south_north[2]~reg0 ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |traffic|led[0]~reg0         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/FPGA/EDA4.3/traffic/traffic.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Apr 03 13:51:44 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic
Info: Found 2 design units, including 1 entities, in source file traffic.vhd
    Info: Found design unit 1: traffic-arch
    Info: Found entity 1: traffic
Info: Found 1 design units, including 1 entities, in source file All traffic.bdf
    Info: Found entity 1: All traffic
Info: Found 2 design units, including 1 entities, in source file DECL7S.vhd
    Info: Found design unit 1: DECL7S-ONE
    Info: Found entity 1: DECL7S
Info: Elaborating entity "traffic" for the top level hierarchy
Warning: VHDL Process Statement warning at traffic.vhd(48): signal "east_west" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at traffic.vhd(49): signal "east_west" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at traffic.vhd(50): signal "south_north" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at traffic.vhd(51): signal "south_north" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 119 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 38 output pins
    Info: Implemented 79 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Tue Apr 03 13:51:46 2007
    Info: Elapsed time: 00:00:03