icpld.map.qmsg

This file is gotten from the web.

{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "INTr\[3\] icpld.v(23) " "Warning (10034): Output port \"INTr\[3\]\" at icpld.v(23) has no driver" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 23 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "INTr\[2\] icpld.v(23) " "Warning (10034): Output port \"INTr\[2\]\" at icpld.v(23) has no driver" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 23 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "INTr\[1\] icpld.v(23) " "Warning (10034): Output port \"INTr\[1\]\" at icpld.v(23) has no driver" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 23 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "INTr\[0\] icpld.v(23) " "Warning (10034): Output port \"INTr\[0\]\" at icpld.v(23) has no driver" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 23 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "PS2KB_CLOCK " "Warning: The bidir \"PS2KB_CLOCK\" has no source; inserted an always disabled tri-state buffer." {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 17 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "PS2MOUSE_CLOCK " "Warning: The bidir \"PS2MOUSE_CLOCK\" has no source; inserted an always disabled tri-state buffer." {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 17 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "FPGA_DATA\[0\] " "Warning: The bidir \"FPGA_DATA\[0\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 21 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "FPGA_DATA\[1\] " "Warning: The bidir \"FPGA_DATA\[1\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 21 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "FPGA_DATA\[2\] " "Warning: The bidir \"FPGA_DATA\[2\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 21 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "FPGA_DATA\[3\] " "Warning: The bidir \"FPGA_DATA\[3\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 21 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "FPGA_DATA\[4\] " "Warning: The bidir \"FPGA_DATA\[4\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 21 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "FPGA_DATA\[5\] " "Warning: The bidir \"FPGA_DATA\[5\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 21 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "FPGA_DATA\[6\] " "Warning: The bidir \"FPGA_DATA\[6\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 21 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "FPGA_DATA\[7\] " "Warning: The bidir \"FPGA_DATA\[7\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 21 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "TXD_CPLD GND " "Warning: Pin \"TXD_CPLD\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 16 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_CTRL\[0\] GND " "Warning: Pin \"LCD_CTRL\[0\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 18 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_CTRL\[1\] GND " "Warning: Pin \"LCD_CTRL\[1\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 18 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_CTRL\[2\] GND " "Warning: Pin \"LCD_CTRL\[2\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 18 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_DATA\[0\] GND " "Warning: Pin \"LCD_DATA\[0\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 19 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_DATA\[1\] GND " "Warning: Pin \"LCD_DATA\[1\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 19 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_DATA\[2\] GND " "Warning: Pin \"LCD_DATA\[2\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 19 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_DATA\[3\] GND " "Warning: Pin \"LCD_DATA\[3\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 19 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_DATA\[4\] GND " "Warning: Pin \"LCD_DATA\[4\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 19 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_DATA\[5\] GND " "Warning: Pin \"LCD_DATA\[5\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 19 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_DATA\[6\] GND " "Warning: Pin \"LCD_DATA\[6\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 19 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_DATA\[7\] GND " "Warning: Pin \"LCD_DATA\[7\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 19 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "INTr\[0\] GND " "Warning: Pin \"INTr\[0\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 23 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "INTr\[1\] GND " "Warning: Pin \"INTr\[1\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 23 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "INTr\[2\] GND " "Warning: Pin \"INTr\[2\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 23 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "INTr\[3\] GND " "Warning: Pin \"INTr\[3\]\" stuck at GND" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 23 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "16 " "Warning: Design contains 16 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "RAM_ADDR_LATCH\[0\] " "Warning: No output dependent on input pin \"RAM_ADDR_LATCH\[0\]\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "RAM_ADDR_LATCH\[1\] " "Warning: No output dependent on input pin \"RAM_ADDR_LATCH\[1\]\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "RAM_ADDR_LATCH\[2\] " "Warning: No output dependent on input pin \"RAM_ADDR_LATCH\[2\]\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "FREGSEL_LATCH_EN " "Warning: No output dependent on input pin \"FREGSEL_LATCH_EN\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 7 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "RXD_CPLD " "Warning: No output dependent on input pin \"RXD_CPLD\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 15 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "RS_CLK " "Warning: No output dependent on input pin \"RS_CLK\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 15 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "PS2KB_DATA " "Warning: No output dependent on input pin \"PS2KB_DATA\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 15 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "PS2MOUSE_DATA " "Warning: No output dependent on input pin \"PS2MOUSE_DATA\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 15 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "FPGA_ADDR\[0\] " "Warning: No output dependent on input pin \"FPGA_ADDR\[0\]\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 20 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "FPGA_ADDR\[1\] " "Warning: No output dependent on input pin \"FPGA_ADDR\[1\]\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 20 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "FPGA_ADDR\[2\] " "Warning: No output dependent on input pin \"FPGA_ADDR\[2\]\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 20 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "FPGA_ADDR\[3\] " "Warning: No output dependent on input pin \"FPGA_ADDR\[3\]\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 20 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "FPGA_ADDR\[4\] " "Warning: No output dependent on input pin \"FPGA_ADDR\[4\]\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 20 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "FPGA_ADDR\[5\] " "Warning: No output dependent on input pin \"FPGA_ADDR\[5\]\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 20 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "FPGA_ADDR\[6\] " "Warning: No output dependent on input pin \"FPGA_ADDR\[6\]\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 20 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "FPGA_ADDR\[7\] " "Warning: No output dependent on input pin \"FPGA_ADDR\[7\]\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 20 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "159 " "Info: Implemented 159 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "36 " "Info: Implemented 36 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "44 " "Info: Implemented 44 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "10 " "Info: Implemented 10 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "69 " "Info: Implemented 69 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 61 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 61 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "117 " "Info: Allocated 117 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 04 16:28:51 2008 " "Info: Processing ended: Tue Mar 04 16:28:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}